PCMPESTRM instruction (SSE4.2)

Forms

Every encoding of PCMPESTRM that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPESTRM xmm, m128, imm8` PCMPESTRM_XMMdq_MEMdq_IMMb	`66 0F 3A 60 /r ib`	SSE4.2
`PCMPESTRM xmm, xmm, imm8` PCMPESTRM_XMMdq_XMMdq_IMMb	`66 0F 3A 60 /r ib`	SSE4.2
`PCMPESTRM xmm, m128, imm8` 64-bit mode only PCMPESTRM64_XMMdq_MEMdq_IMMb	`66 REX.W 0F 3A 60 /r ib`	SSE4.2
`PCMPESTRM xmm, xmm, imm8` 64-bit mode only PCMPESTRM64_XMMdq_XMMdq_IMMb	`66 REX.W 0F 3A 60 /r ib`	SSE4.2

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the forms only in 64-bit mode

n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |EAX| and |EDX|, at most n,
# the count of imm8[0] (not of imm8[3])
la = min(abs(signed(eax)), n)
lb = min(abs(signed(edx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
    v = 0
    for j in range(n):
        if r >> j & 1:
            v |= m << w * j
    xmm0.write(v)
else:
    xmm0.write(r)      # the bits alone
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0
# bits 128 and up of xmm0 are unchanged

Run on AMD Zen 5 (EPYC 9645): 14 cases.

Forms only in 64-bit mode

n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
# the lengths: |RAX| and |RDX| (REX.W), at
# most n, the count of imm8[0]
la = min(abs(signed(rax)), n)
lb = min(abs(signed(rdx)), n)
a = xmm1.read()
b = src2.read()
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
    v = 0
    for j in range(n):
        if r >> j & 1:
            v |= m << w * j
    xmm0.write(v)
else:
    xmm0.write(r)      # the bits alone
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0
# bits 128 and up of xmm0 are unchanged

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPESTRM xmm, xmm/m128, imm8`
`xmm`	explicit	read
`xmm/m128`	explicit	read
`imm8`	explicit	read
`rAX`	implicit	read
`rDX`	implicit	read
`XMM0`	implicit	write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
M	M	M	0	0	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPESTRM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpestrm` `__m128i _mm_cmpestrm(__m128i A, int LA, __m128i B, int LB, const int M)`	`PCMPESTRM xmm, xmm, imm8` Legacy -msse4.1 -msse4.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE42` SSE4.2	SSE4.2 `CPUID.01H:ECX[20]` SSE4.2	Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

PCMPESTRM