PCMPGTB instruction (MMX, SSE2)

PCMPGTB compares bytes as signed integers, 16 pairs in an XMM register or 8 in an MMX register, and sets each destination byte to FFh where the destination’s byte is the greater and to 00h otherwise. The MMX form came with MMX and the XMM form with SSE2, so every x86-64 processor has both. On Zen 5, the recorded pcmpgtb xmm1, xmm2 found 7Fh greater than FFh (127 against -1) and 00h greater than 80h (0 against -128), and gave 00h for equal bytes; bits 255:128 of the register kept their value, as with every legacy SSE instruction (see mixing SSE and AVX).

The other orderings

PCMPEQB gives equality; the rest is built:

Less-than swaps the operands, often at the cost of a MOVDQA copy, since the legacy form overwrites its first operand.
Greater or equal inverts less-than with a PXOR against all ones, or swaps the inputs of the select that follows.
Unsigned bytes take a detour, described on the PMINUB page: for b[i] > c[i] over uint8_t, GCC 14 at -O2 subtracts with unsigned saturation and compares with zero, Clang 23 takes PMINUB, PCMPEQB and PXOR.

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Selects. a[i] = b[i] > c[i] ? -1 : 0 over int8_t is one compare per 16 bytes. The signed maximum, b[i] > c[i] ? b[i] : c[i], adds PAND, PANDN and POR, because PMAXSB came only with SSE4.1; with -march=x86-64-v2 it is one PMAXSB.
Sign masks. Bytes have no arithmetic shift, so b[i] < 0 ? -1 : 0 compares a zeroed register with the data: 0 is greater exactly where a byte is negative.

A register is never greater than itself, so the compare with one register twice gives zero; which processors take that as a zeroing idiom the optimization guide covers, and compilers zero registers with PXOR. AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). A memory operand of the XMM form must be aligned to 16 bytes. VPCMPGTB is the VEX and EVEX form, the EVEX one writing a mask register.

Forms

Every encoding of PCMPGTB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPGTB mm, m64` PCMPGTB_MMXq_MEMq	`NP 0F 64 /r`	MMX
`PCMPGTB mm, mm` PCMPGTB_MMXq_MMXq	`NP 0F 64 /r`	MMX
`PCMPGTB xmm, m128` PCMPGTB_XMMdq_MEMdq	`66 0F 64 /r`	SSE2
`PCMPGTB xmm, xmm` PCMPGTB_XMMdq_XMMdq	`66 0F 64 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPGTB mm, mm/m64

for i in range(8):
    sa = mm1.sb[i]
    sb = src2.sb[i]
    mm1.b[i] = -1 if sa > sb else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPGTB xmm, xmm/m128

for i in range(16):
    sa = xmm1.sb[i]
    sb = src2.sb[i]
    xmm1.b[i] = -1 if sa > sb else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPGTB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPGTB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPGTB mm, m64: mmx-mem
PCMPGTB mm, mm: none in XED
PCMPGTB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPGTB mm, mm/m64: may abort a TSX transaction
PCMPGTB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPGTB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpgt_epi8` `__m128i _mm_cmpgt_epi8(__m128i __a, __m128i __b)`	`PCMPGTB xmm, xmm` Legacy -msse2
`_mm_cmpgt_pi8` `__m64 _mm_cmpgt_pi8(__m64 __m1, __m64 __m2)`	`PCMPGTB xmm, xmm` Legacy -msse2
`_mm_cmplt_epi8` `__m128i _mm_cmplt_epi8(__m128i __a, __m128i __b)`	`PCMPGTB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

The other orderings#

In compiled code#