PCMPGTD instruction (MMX, SSE2)

PCMPGTD compares doublewords as signed integers, 4 pairs in an XMM register or 2 in an MMX register, and sets each destination doubleword to FFFFFFFFh where the destination’s element is the greater and to zero otherwise. On Zen 5, the recorded pcmpgtd xmm8, xmm15 found 80000000h not greater than 7FFFFFFFh, the most negative value against the largest, and 8 not greater than 8; pcmpgtd mm3, [mem] found 1 greater than FFFFFFFFh, which is -1. Bits 255:128 of the XMM register kept their value (see mixing SSE and AVX). PCMPGTB describes how the other orderings are built from greater-than, and VPCMPGTD, the VEX and EVEX form, the unsigned detours.

The baseline’s doubleword tool

SSE2 has no doubleword minimum, maximum or sign extension; PCMPGTD stands in for them. In our builds at -O2 for the x86-64 baseline, over int32_t arrays:

Maximum. b[i] > c[i] ? b[i] : c[i] is PCMPGTD and a select with PAND, PANDN and POR in GCC 14 and Clang 23, where -march=x86-64-v2 has PMAXSD. b[i] > 0 ? b[i] : 0 needs only the compare against zero and a PAND.
Sign extension. Widening to int64_t compares a zeroed register with the data, which gives all ones exactly for the negative elements, and interleaves values and signs with PUNPCKLDQ, and PUNPCKHDQ for the upper half in GCC; -v2 uses PMOVSXDQ.
Sign function. (b[i] > 0) - (b[i] < 0) is two PCMPGTDs against zero, one in each direction, and a PSUBD of the two masks, since each mask is -1 where it holds.
Unsigned order. For uint32_t, both move the values by 80000000h first, GCC subtracting it with PSUBD and Clang flipping the sign bit with PXOR, which is the same thing.

A register is never greater than itself, so PCMPGTD with one register twice gives zero; which cores treat that as a zeroing idiom the optimization guide covers. AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes.

Forms

Every encoding of PCMPGTD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPGTD mm, m64` PCMPGTD_MMXq_MEMq	`NP 0F 66 /r`	MMX
`PCMPGTD mm, mm` PCMPGTD_MMXq_MMXq	`NP 0F 66 /r`	MMX
`PCMPGTD xmm, m128` PCMPGTD_XMMdq_MEMdq	`66 0F 66 /r`	SSE2
`PCMPGTD xmm, xmm` PCMPGTD_XMMdq_XMMdq	`66 0F 66 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Every doubleword works alike: 2 and 4 doublewords in the mm and xmm forms.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPGTD mm, mm/m64

for i in range(2):
    sa = mm1.sd[i]
    sb = src2.sd[i]
    mm1.d[i] = -1 if sa > sb else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPGTD xmm, xmm/m128

for i in range(4):
    sa = xmm1.sd[i]
    sb = src2.sd[i]
    xmm1.d[i] = -1 if sa > sb else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPGTD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPGTD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPGTD mm, m64: mmx-mem
PCMPGTD mm, mm: none in XED
PCMPGTD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPGTD mm, mm/m64: may abort a TSX transaction
PCMPGTD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPGTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpgt_epi32` `__m128i _mm_cmpgt_epi32(__m128i __a, __m128i __b)`	`PCMPGTD xmm, xmm` Legacy -msse2
`_mm_cmpgt_pi32` `__m64 _mm_cmpgt_pi32(__m64 __m1, __m64 __m2)`	`PCMPGTD xmm, xmm` Legacy -msse2
`_mm_cmplt_epi32` `__m128i _mm_cmplt_epi32(__m128i __a, __m128i __b)`	`PCMPGTD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

The baseline’s doubleword tool#