PCMPGTQ

PCMPGTQ compares the two quadwords of an XMM register with those of another register or of memory, as signed integers, and sets each destination quadword to all ones where it was the greater and to zero otherwise. It is the one integer compare of SSE4.2: its equality partner, PCMPEQQ, came a step earlier with SSE4.1, so a processor can have the one without the other, and Intel’s optimization manual reminds that the SSE4.2 bit must be checked before using it (Section 14.1). Both are part of x86-64-v2. There is no MMX form.

The comparison is signed. On Zen 5, the recorded pcmpgtq xmm1, [mem] found 8000000000000000h, the most negative value, not greater than 7FFFFFFFFFFFFFFFh, and pcmpgtq xmm4, xmm4 cleared both quadwords: a value is never greater than itself (see zeroing idioms). Bits 255:128 of the destination kept their value.

Before SSE4.2#

For a[i] = b[i] > c[i] ? -1 : 0 over int64_t, GCC 14 at -O2 for the SSE2 baseline keeps the loop scalar, with CMP, SETG and NEG. Clang 23 vectorizes it from doubleword compares: it flips the sign bit of the low halves with PXOR, so that a signed PCMPGTD orders them as unsigned, compares the high halves for greater and for equal, and combines the results with PSHUFD, PAND and POR, about ten instructions per vector. With -march=x86-64-v2, both emit one PCMPGTQ.

Maximum and unsigned order#

• Maximum. SSE has no quadword maximum before AVX-512’s VPMAXSQ. At -v2, b[i] > c[i] ? b[i] : c[i] is PCMPGTQ and a blend by its mask: PBLENDVB in GCC, BLENDVPD in Clang. Intel’s optimization manual contrasts the same pair in AVX2 with the single AVX-512 instruction (Section 17.13.1).
• Unsigned. For uint64_t, both move the range down by 8000000000000000h before comparing signed: GCC subtracts it with PSUBQ, Clang flips the top bit with PXOR, which is the same thing.

AMD’s latency spreadsheet for Zen 5 gives PCMPGTQ two cycles and two per cycle, where the byte, word and doubleword compares take one cycle at four per cycle. A memory operand must be aligned to 16 bytes. VPCMPGTQ is the VEX and EVEX form.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    sa = xmm1.sq[i]
    sb = src2.sq[i]
    xmm1.q[i] = -1 if sa > sb else 0
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPGTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE4.2 instructions

• CRC32
• PCMPESTRI
• PCMPESTRM
• PCMPISTRI
• PCMPISTRM