PCMPGTW instruction (MMX, SSE2)

PCMPGTW compares words as signed 16-bit integers, 8 pairs in an XMM register or 4 in an MMX register, and sets each word of the destination to FFFFh where the destination’s word is the greater and to 0000h otherwise. PCMPGTB describes the family: how the other orderings are built from greater-than and equality, and the selects that follow. On Zen 5, the recorded pcmpgtw xmm8, xmm15 gave FFFFh for 7FFFh against 0001h and for 0000h against 8000h (0 against -32768), 0000h for 8000h against 0001h, and 0000h for equal words, and left bits 255:128 of the register as they were.

What words change

Words, unlike bytes, have an arithmetic shift, and that changes what the compilers pick. In our builds at -O2 for the x86-64 baseline, over arrays of int16_t and uint16_t:

Sign masks. For s[i] < 0 ? -1 : 0, Clang 23 shifts each word right by 15 with PSRAW; GCC 14 still compares a zeroed register with the data, as for bytes.
Sign extension. Widening int16_t to int32_t without SSE4.1, GCC builds the high halves with the same compare against zero and interleaves data and signs with PUNPCKLWD and PUNPCKHWD; Clang interleaves each word with itself and shifts the doublewords right by 16 with PSRAD. PMOVSXWD does it in one step.
Unsigned words. For us[i] > ut[i], Clang flips the sign bit of both operands with PXOR against 8000h, which maps the unsigned order onto the signed one, and uses PCMPGTW. GCC subtracts with unsigned saturation, PSUBUSW, and tests the difference for zero with two PCMPEQWs, the second inverting the first. With -march=x86-64-v2 Clang turns to PMINUW, PCMPEQW and an inversion.

AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. The MMX form came with MMX and the XMM form with SSE2, whose memory operand must be aligned to 16 bytes; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX). VPCMPGTW is the VEX and EVEX form, the EVEX one writing a mask register.

Forms

Every encoding of PCMPGTW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCMPGTW mm, m64` PCMPGTW_MMXq_MEMq	`NP 0F 65 /r`	MMX
`PCMPGTW mm, mm` PCMPGTW_MMXq_MMXq	`NP 0F 65 /r`	MMX
`PCMPGTW xmm, m128` PCMPGTW_XMMdq_MEMdq	`66 0F 65 /r`	SSE2
`PCMPGTW xmm, xmm` PCMPGTW_XMMdq_XMMdq	`66 0F 65 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PCMPGTW mm, mm/m64

for i in range(4):
    sa = mm1.sw[i]
    sb = src2.sw[i]
    mm1.w[i] = -1 if sa > sb else 0
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PCMPGTW xmm, xmm/m128

for i in range(8):
    sa = xmm1.sw[i]
    sb = src2.sw[i]
    xmm1.w[i] = -1 if sa > sb else 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCMPGTW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PCMPGTW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PCMPGTW mm, m64: mmx-mem
PCMPGTW mm, mm: none in XED
PCMPGTW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PCMPGTW mm, mm/m64: may abort a TSX transaction
PCMPGTW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPGTW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmpgt_epi16` `__m128i _mm_cmpgt_epi16(__m128i __a, __m128i __b)`	`PCMPGTW xmm, xmm` Legacy -msse2
`_mm_cmpgt_pi16` `__m64 _mm_cmpgt_pi16(__m64 __m1, __m64 __m2)`	`PCMPGTW xmm, xmm` Legacy -msse2
`_mm_cmplt_epi16` `__m128i _mm_cmplt_epi16(__m128i __a, __m128i __b)`	`PCMPGTW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

What words change#