PCMPISTRI

PCMPISTRI compares two strings of up to 16 bytes or 8 words, each ending at its first null element, and returns an index in ECX: of the lowest or, with bit 6 of the control byte, the highest result bit set, or 16 (8 for words) if none is. Bits 1:0 choose signed or unsigned bytes or words, bits 5:4 can invert the result. PCMPESTRI takes the lengths in EAX and EDX instead of looking for nulls, and PCMPISTRM returns the result as a mask in XMM0.

The four comparisons#

Bits 3:2 choose what the first operand, the pattern, means for the second, the text:

• equal any (00): text bytes that occur in the pattern, a set as for strpbrk;
• ranges (01): text bytes inside one of the pattern’s pairs, such as “az”, “AZ”, “09”;
• equal each (10): position by position, as for strcmp;
• equal ordered (11): positions where the pattern starts, as for strstr.

CF is set when any result bit is, ZF when the text holds a null, SF when the pattern does, and OF is result bit 0: one PCMPISTRI says both where a match is and whether the text ended.

Traps#

Equal ordered also reports a match that runs off the end of the 16 bytes: for the pattern “abc” in “xxabcxxxxxxxxxab”, asked for the highest index, Zen 5 returned 14, where only “ab” fits, so a search loads the text again from such an index. With an empty pattern, Intel’s manual sets every bit and AMD’s only those up to the text’s length; Zen 5 did as Intel’s manual says.

The memory operand need not be aligned, but all 16 bytes are read, nulls or not, so a load near the end of a string can touch the next page. Intel’s optimization manual advises padding buffers by 16 bytes (Section 14.2.1).

From C#

The intrinsics need -msse4.2 and return one result each: _mm_cmpistri the index, _mm_cmpistrc and _mm_cmpistrz the flags. For a loop that uses all three, GCC 14 at -O2 shares one PCMPISTRI between the index and CF but runs PCMPISTRM for ZF, and Clang 23 runs PCMPISTRI once per intrinsic.

Speed#

AMD’s Zen 5 guide lists PCMPISTRI as four macro-ops, one every two cycles, and PCMPESTRI as eight or more. Intel’s optimization manual advises against computing the next address from ECX inside a loop (Section 14.3.1, Tuning Suggestion 4).

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = 8 if imm8 & 1 else 16  # words, bytes
w = 128 // n               # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0  # signed
a = xmm1.read()
b = src2.read()
la = lb = n            # lengths: up to the
for i in range(n):     # first null element
    if a >> w * i & m == 0 and la == n:
        la = i
    if b >> w * i & m == 0 and lb == n:
        lb = i
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n):     # bit j: src2's
    y = (b >> w * j & m ^ k) - k  # element j
    bit = 0
    if agg == 0:       # equal any: y is
        for i in range(la):  # in xmm1
            x = (a >> w * i & m ^ k) - k
            if j < lb and x == y:
                bit = 1
    elif agg == 1:     # ranges: y is in
        for i in range(0, la - 1, 2):
            t = w * i  # a pair's range
            lo = (a >> t & m ^ k) - k
            hi = (a >> t + w & m ^ k) - k
            if j < lb and lo <= y <= hi:
                bit = 1
    elif agg == 2:     # equal each
        x = (a >> w * j & m ^ k) - k
        if j < la and j < lb:
            bit = x == y
        else:          # 1 past both ends
            bit = j >= la and j >= lb
    else:              # equal ordered: xmm1
        bit = 1        # from element j on;
        # what would fall past the end of the
        # register matches, and an empty xmm1
        # everywhere, as in Intel's manual
        # (AMD's clears these bits)
        for i in range(min(la, n - j)):
            x = (a >> w * i & m ^ k) - k
            u = j + i
            z = (b >> w * u & m ^ k) - k
            if u >= lb or x != z:
                bit = 0
    r |= bit << j
p = imm8 >> 4 & 3
if p == 1:             # negated
    r ^= (1 << n) - 1
elif p == 3:           # negated within src2
    r ^= (1 << lb) - 1
idx = n                # none set
for j in range(n):     # imm8[6]: the
    if r >> j & 1:     # highest set bit,
        if imm8 & 0x40 or idx == n:
            idx = j    # else the lowest
ecx = idx              # bits 63:32 cleared
cf = r != 0
zf = lb < n            # src2 is short
sf = la < n            # xmm1 is short
of = r & 1
af = pf = 0

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PCMPISTRI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE4.2 instructions

• CRC32
• PCMPESTRI
• PCMPESTRM
• PCMPGTQ
• PCMPISTRM