Instruction
PCMPISTRM
Compares two zero-terminated strings in XMM registers as an immediate says, returning a bit or byte mask in XMM0.
- Extensions
- Forms
- 2 (2 Legacy)
- Data
- Intel XED v2026.08.23
PCMPISTRM makes the same comparison as PCMPISTRI, of a pattern in the first operand and a text in the second, each ending at its first null, but returns the result as a mask in XMM0 instead of an index in ECX. XMM0 is fixed, whatever the operands are. PCMPESTRM takes the lengths from EAX and EDX instead.
Two shapes of mask
Bit 6 of the control byte, which picks the lowest or highest index in PCMPISTRI, picks the shape of the mask here:
- 0, bits: one bit per element in the low 16 bits of XMM0 (8 for
words), the rest of the 128 bits cleared.
_mm_cvtsi128_si32gets them into a general register with a MOVD, ready for TZCNT or POPCNT. - 1, elements: each element of XMM0 all ones or all zeros, bytes or words as bit 0 of the control byte says.
The element mask is made for PBLENDVB, which also reads its mask from XMM0. Intel’s optimization manual converts text to upper case that way (Example 14-12): ranges “az” give the mask of the lower-case letters, and PBLENDVB takes those bytes from the text minus 20H. GCC 14 and Clang 23 at -O2 compile such code with no move between the two instructions.
Flags and the rest of the register
The flags are PCMPISTRI’s: CF when any result bit is set, ZF when the text holds a null, SF when the pattern does, OF for result bit 0. Zen 5 recorded the legacy form keeping bits 128 and up of the register that holds XMM0; the VEX form, VPCMPISTRM, clears them.
Speed
AMD’s Zen 5 guide lists PCMPISTRM as three macro-ops, of which a core starts one every seven cycles, and four with a memory operand, one every two cycles. Like PCMPISTRI, it reads all 16 bytes of a memory operand whatever the nulls, which matters near the end of a page.
Forms
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
n = 8 if imm8 & 1 else 16 # words, bytes
w = 128 // n # bits each
m = (1 << w) - 1
k = 1 << w - 1 if imm8 & 2 else 0 # signed
a = xmm1.read()
b = src2.read()
la = lb = n # lengths: up to the
for i in range(n): # first null element
if a >> w * i & m == 0 and la == n:
la = i
if b >> w * i & m == 0 and lb == n:
lb = i
agg = imm8 >> 2 & 3
# (v >> w * i & m ^ k) - k: element i of v,
# sign-extended where k is its sign bit
r = 0
for j in range(n): # bit j: src2's
y = (b >> w * j & m ^ k) - k # element j
bit = 0
if agg == 0: # equal any: y is
for i in range(la): # in xmm1
x = (a >> w * i & m ^ k) - k
if j < lb and x == y:
bit = 1
elif agg == 1: # ranges: y is in
for i in range(0, la - 1, 2):
t = w * i # a pair's range
lo = (a >> t & m ^ k) - k
hi = (a >> t + w & m ^ k) - k
if j < lb and lo <= y <= hi:
bit = 1
elif agg == 2: # equal each
x = (a >> w * j & m ^ k) - k
if j < la and j < lb:
bit = x == y
else: # 1 past both ends
bit = j >= la and j >= lb
else: # equal ordered: xmm1
bit = 1 # from element j on;
# what would fall past the end of the
# register matches, and an empty xmm1
# everywhere, as in Intel's manual
# (AMD's clears these bits)
for i in range(min(la, n - j)):
x = (a >> w * i & m ^ k) - k
u = j + i
z = (b >> w * u & m ^ k) - k
if u >= lb or x != z:
bit = 0
r |= bit << j
p = imm8 >> 4 & 3
if p == 1: # negated
r ^= (1 << n) - 1
elif p == 3: # negated within src2
r ^= (1 << lb) - 1
# imm8[6]: each bit made an element of ones,
# words where imm8[0] is set (whatever
# imm8[1], which Intel's table names)
if imm8 & 0x40:
v = 0
for j in range(n):
if r >> j & 1:
v |= m << w * j
xmm0.write(v)
else:
xmm0.write(r) # the bits alone
cf = r != 0
zf = lb < n # src2 is short
sf = la < n # xmm1 is short
of = r & 1
af = pf = 0
# bits 128 and up of xmm0 are unchangedRun on AMD Zen 5 (EPYC 9645): 14 cases.
Operands
| Operand | Kind | Action |
|---|---|---|
PCMPISTRM xmm, xmm/m128, imm8 | ||
xmm | explicit | read |
xmm/m128 | explicit | read |
imm8 | explicit | read |
XMM0 | implicit | write |
RFLAGS | implicit | write |
Flags
| OF | SF | ZF | AF | PF | CF |
|---|---|---|---|---|---|
| All forms | |||||
| M | M | M | 0 | 0 | M |
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- All forms
SSE_TYPE_4
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to PCMPISTRM, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cmpistrm
__m128i _mm_cmpistrm(__m128i A, __m128i B, const int M) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
SSE42 | SSE4.2 | Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them. |
More SSE4.2 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s
-marchfeature sets and AMD’s Processor Programming References, which the page of each processor cites. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-269 (PCMPISTRM)
- AMD64 Architecture Programmer's Manual, Volume 4: 128-Bit and 256-Bit Media Instructions (26568, rev. 3.25, November 2021), Wayback Machine copy of AMD's PDF
- Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)
- Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.