PCONFIG instruction (PCONFIG)

Forms

Every encoding of PCONFIG that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PCONFIG` not in 64-bit mode PCONFIG	`NP 0F 01 C5`	PCONFIG
`PCONFIG` 64-bit mode only PCONFIG64	`NP 0F 01 C5`	PCONFIG

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`PCONFIG`
Ice Lake, Alder Lake, Sapphire Rapids	100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

Forms only in 64-bit mode

ok = cpuid_leaf(7, 0)[3] >> 18 & 1
if not ok or CPL > 0:
    fault(UD)                # #UD, not #GP, outside CPL 0
n = eax                      # the leaf
if n > 2:
    fault(GP, 0)
if not pconfig_target(1 if n == 0 else 2):
    fault(GP, 0)             # TME-MK (1) or TSE (2) absent
if n == 0:                   # MKTME_KEY_PROGRAM
    act = msr[IA32_TME_ACTIVATE]
    k = act >> 32 & 0xF      # KeyID bits
    if act & 3 != 3 or not k:
        fault(GP, 0)         # TME-MK not locked and on
    cap = msr[IA32_TME_CAPABILITY]
    maxk = cap >> 36 & 0x7FFF
    algs = act >> 48         # the algorithms activated
else:                        # TSE_KEY_PROGRAM(_WRAPPED)
    cap = msr[IA32_TSE_CAPABILITY]
    maxk = cap >> 36 & 0x7FFF
    algs = cap & 0xFFFF
if n < 2:                    # the 192-byte structure at RBX
    a = rbx
    if a & 0xFF:
        fault(GP, 0)         # 256-byte aligned
    key = load(a, 16)        # KEYID
    ctl = load(a + 2, 32)    # KEYID_CTRL
    cmd = ctl & 0xFF
    alg = ctl >> 8 & 0xFFFF
    if ctl >> 24 or cmd > 3 - 2 * n:
        fault(GP, 0)         # reserved bits, or no command:
                             # 0 to 3 (TME-MK), 0 or 1 (TSE)
else:                        # control in RBX, bind structure
    key = rbx & 0xFFFF       # at RCX (PBNDKB's output)
    alg = rbx >> 24 & 0xFFFF
    if rbx >> 16 & 0xFF or rcx & 0xFF:
        fault(GP, 0)
if key > maxk or n == 0 and key == 0:
    fault(GP, 0)             # a KeyID past the last
if n == 0:
    p = act >> 36 & 0xF      # those TDX keeps outside SEAM
    if key >> k:
        fault(GP, 0)
    if not seam and p and key >> k - p:
        fault(GP, 0)
if alg & alg - 1 or not alg & algs:
    fault(GP, 0)             # one algorithm, an activated one
e = leaf_function(n)         # the key table updated for KEYID:
                             # 0, or the platform's reason; leaf
                             # 2 first checks the bind structure
                             # (#GP(0)) and unwraps the keys
rax = e
zf = e != 0
cf = pf = af = of = sf = 0

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no PCONFIG, and every one raised an exception.

Forms not in 64-bit mode

ok = cpuid_leaf(7, 0)[3] >> 18 & 1
if not ok or CPL > 0:
    fault(UD)                # #UD, not #GP, outside CPL 0
n = eax                      # the leaf
if n > 2:
    fault(GP, 0)
if n > 0:
    fault(GP, 0)             # TSE's leaves: 64-bit mode alone
e = leaf_function(n)         # MKTME_KEY_PROGRAM, with the
                             # checks of 64-bit mode on the
                             # structure at DS:EBX
eax = e
zf = e != 0
cf = pf = af = of = sf = 0

Not run on a processor: this is PCONFIG outside 64-bit mode, and the probe runs in 64-bit mode.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PCONFIG` not in 64-bit mode
`EAX`	implicit	read, write
`rBX`	implicit	conditional read, write
`rCX`	implicit	conditional read, write
`rDX`	implicit	conditional read, write
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	0	0

Attributes

What else XED records about the forms. How to read.

All forms: privileged: CPL 0 only

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PCONFIG` PCONFIG	PCONFIG `CPUID.(EAX=07H,ECX=0):EDX[18]` PCONFIG	Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest