PDEP

PDEP scatters the low bits of its source to the positions of the 1 bits of a mask, in order: bit 0 of the source goes to the lowest 1 of the mask, bit 1 to the next one, and so on. Every position where the mask has a 0 is cleared, and source bits beyond the mask’s number of ones are dropped. Depositing 0b101 into the mask 0xF0 gives 0x50. PEXT does the reverse, gathering the bits at the mask’s positions into the low bits, so PEXT of PDEP(x, m) with the same mask m gives back the low bits of x, as many as m has ones.

Operand order#

In Intel syntax the source comes second and the mask third: pdep rax, rbx, rcx deposits RBX into the places of RCX, and only the mask may be in memory. The intrinsics _pdep_u32(src, mask) and _pdep_u64(src, mask) take them in the same order. There are 32- and 64-bit forms, no 16-bit one, and no flag changes.

Uses#

• The index of the n-th set bit of x, counting from 0: deposit the single bit 1 << n into the mask x and count the trailing zeros. GCC 14 and Clang 23 at -O2 compile _tzcnt_u64(_pdep_u64(1ULL << n, x)) to SHLX, PDEP and TZCNT; if x has n or fewer set bits, the result is 64.
• Interleaving: _pdep_u64(x, 0x5555555555555555) spreads x over the even bits and _pdep_u64(y, 0xAAAAAAAAAAAAAAAA) y over the odd ones; their OR is the Morton code of the point (x, y).
• Widening a bit mask: PDEP of an 8-bit mask into 0x0101010101010101 puts each bit at the bottom of its own byte, and a multiplication by 0xFF turns each byte into 0x00 or 0xFF.

Neither compiler finds PDEP in plain C.

Speed differs between processors#

Intel’s optimization manual lists PDEP with MUL and IMUL among the instructions of the one “slow integer” unit of Golden Cove (Table 2-4). AMD’s Zen 5 guide says that Zen 5 runs PDEP and PEXT natively in three of its ALUs, three per cycle with a latency of three cycles, and tells software that chooses between code for fast and slow PDEP to take the fast code there (Section 2.10.2).

PDEP belongs to BMI2, part of x86-64-v3; APX adds an EVEX form that reaches its new registers.

In the optimization guide

What the optimization guide says about PDEP, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Golden Cove and Raptor Cove

• Integer execution: Port 1 alone runs the slower integer operations: multiplication, PDEP and PEXT, popcnt, bsr, crc32 and the double shifts with an immediate count, which LLVM’s models give a latency of three cycles and one per cycle.

Skylake to Cooper Lake

• Integer execution: Port 1 alone runs integer multiplication, PDEP and PEXT, popcnt, lzcnt, tzcnt, bsf, bsr and the double shifts, with a latency of three cycles and one a cycle in LLVM’s models, as on Golden Cove.

Zen and Zen+

• Integer execution: PDEP and PEXT are microcoded, in AMD’s spreadsheet and in LLVM’s model, though the core supports BMI2; code with a choice uses shifts and masks instead.

Zen 2

• Integer execution: PDEP and PEXT are microcoded, as in LLVM’s model, though CPUID reports BMI2; Zen 3 runs them on an ALU in three cycles.

Zen 3

• Integer execution: PDEP and PEXT run natively on ALU 1, one per cycle with a latency of three cycles; code with a separate path for processors where they are slow, such as Zen 2, should take the fast path.

Zen 4

• Integer execution: PDEP and PEXT run natively on one ALU, one per cycle with a latency of three cycles, against three per cycle on Zen 5; code with a separate path for processors where they are slow should take the fast path.

Zen 5

• Integer execution: PDEP and PEXT run natively, three per cycle with a latency of three cycles; code with a separate path for processors where they are slow should take the fast path.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

s = src.read()
m = mask.read()
r = 0
k = 0                            # the next bit of src, from bit 0 up
for i in range(OSIZE):
    if m >> i & 1:
        r |= (s >> k & 1) << i   # to the place of the next 1 bit of mask
        k += 1
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PDEP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• BZHI
• MULX
• PEXT
• RORX
• SARX
• SHLX
• SHRX

More APX instructions

• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI
• MOVRS
• MUL
• MULX
• NEG
• NOT
• OR
• PEXT
• POP2
• POP2P
• POPCNT
• POPP
• PUSH2
• PUSH2P
• PUSHP
• RCL
• RCR
• RDMSR
• ROL
• ROR
• RORX
• SAR
• SARX
• SBB
• SETcc
• SHL
• SHLD

All 88 APX instructions