x86-64.net

Instruction

PEXT

Extracts the bits of the source at the positions selected by a mask and packs them into the low bits of the destination.

Extensions
Forms
8 (4 VEX, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of PEXT that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
PEXT r32, r32, m32 PEXT_GPR32d_GPR32d_MEMdVEX.LZ.F3.0F38.W0 F5 /rBMI2
PEXT r32, r32, r32 PEXT_GPR32d_GPR32d_GPR32dVEX.LZ.F3.0F38.W0 F5 /rBMI2
PEXT r64, r64, m64 64-bit mode only PEXT_GPR64q_GPR64q_MEMqVEX.LZ.F3.0F38.W1 F5 /rBMI2
PEXT r64, r64, r64 64-bit mode only PEXT_GPR64q_GPR64q_GPR64qVEX.LZ.F3.0F38.W1 F5 /rBMI2
PEXT r32, r32, r32 PEXT_GPR32i32_GPR32i32_GPR32i32_APXEVEX.LLZ.F3.0F38.W0 F5 /rAPX_F + BMI2
PEXT r32, r32, m32 PEXT_GPR32i32_GPR32i32_MEMi32_APXEVEX.LLZ.F3.0F38.W0 F5 /rAPX_F + BMI2
PEXT r64, r64, r64 PEXT_GPR64i64_GPR64i64_GPR64i64_APXEVEX.LLZ.F3.0F38.W1 F5 /rAPX_F + BMI2
PEXT r64, r64, m64 PEXT_GPR64i64_GPR64i64_MEMi64_APXEVEX.LLZ.F3.0F38.W1 F5 /rAPX_F + BMI2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PEXT, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_pext_u32 unsigned int _pext_u32(unsigned int __X, unsigned int __Y)

PEXT r32, r32, r32 VEX.LZ -mbmi2

_pext_u64 unsigned long long _pext_u64(unsigned long long __X, unsigned long long __Y)

PEXT r64, r64, r64 VEX.LZ -mbmi2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
BMI2

BMI2
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
APX_F_BMI2

APX_F + BMI2
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=0):EBX[8] BMI2

Nova Lake, Diamond Rapids

More BMI2 instructions

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.