PEXTRB instruction (SSE4.1)

PEXTRB copies one byte of an XMM register out: into the low byte of a general-purpose register, with every bit above it cleared, or straight to a byte of memory. The low four bits of the immediate pick the byte and the upper four are ignored, so 13h picks byte 3. The index has to be known when the code is assembled; there is no form that takes it from a register.

Zero extension

Compilers write the register form with a 32-bit register, pextrb eax, xmm0, 3, and like any write to a 32-bit register in 64-bit mode it clears the upper half of RAX as well; a REX.W prefix changes nothing. The intrinsic _mm_extract_epi8 therefore returns a value from 0 to 255, and C code that wants the byte as signed has to sign-extend it again.

In compiled code

Reading byte 3 of a vector declared with GCC’s vector_size(16) attribute (v[3]), GCC 14 and Clang 23 at -O2 emit a single PEXTRB once SSE4.1 is enabled. For the SSE2 baseline, which has only the word extract PEXTRW, GCC stores the vector to the stack and reloads the byte with MOVZX, and Clang moves the low doubleword to EAX with MOVD and shifts it right by 24. An index known only at run time goes through memory in both compilers, with or without SSE4.1: the vector is stored and the byte loaded at the index.

The memory form writes exactly one byte, which suits storing single elements to scattered addresses. Intel’s optimization manual shows the doubleword version, PEXTRD, storing the elements of a vector with a stride, one PEXTRD per element (Section 6.4.8).

PEXTRD and PEXTRQ do the same for doublewords and quadwords, and PEXTRW for words. PINSRB goes the other way. PMOVMSKB collects one bit from every byte instead of one whole byte. VPEXTRB, the VEX and EVEX form, also reads only an XMM register: a byte in the upper half of a YMM register needs VEXTRACTI128 first.

In the optimization guide

What the optimization guide says about PEXTRB, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.

Forms

Every encoding of PEXTRB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PEXTRB m8, xmm, imm8` PEXTRB_MEMb_XMMdq_IMMb	`66 0F 3A 14 /r ib`	SSE4.1
`PEXTRB r32, xmm, imm8` PEXTRB_GPR32d_XMMdq_IMMb	`66 0F 3A 14 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: byte imm8 of xmm2 goes to m8.

Example: imm8 = 0x05.

With imm8 = 0x05, m8 receives byte 5 of xmm2: a5.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.b[imm8 & 15])  # zero-extended in a register

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PEXTRB m8, xmm, imm8`
`m8`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read
`PEXTRB r32, xmm, imm8`
`r32`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PEXTRB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi8` `int _mm_extract_epi8(__m128i X, const int N)`	`PEXTRB r32, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Zero extension#

In compiled code#

Related instructions#