PEXTRD instruction (SSE4.1)

PEXTRD copies one doubleword of an XMM register to a 32-bit general-purpose register or to four bytes of memory. Bits 1:0 of the immediate pick the element and the other six are ignored. PEXTRB describes the family: an index fixed when the code is assembled, a memory form that writes only its own bytes, and Intel’s strided store. On Zen 5, pextrd r14d, xmm0, 0x3f took element 3 and cleared bits 63:32 of R14, and pextrd dword ptr [mem], xmm1, 0x6d stored element 1 and left the bytes after it as they were.

Element 0 and the others

Element 0 needs no extract: MOVD copies it, and both compilers use MOVD for v[0]. For elements 1 to 3 of a vector of four ints, GCC 14 at -O2 with -march=x86-64-v2 emits PEXTRD. Clang 23 does so when the vector comes from integer arithmetic, as in (a + b)[2] after a PADDD, but for a vector that arrives as an argument it prints EXTRACTPS, which copies the same 32 bits under a floating-point name: an LLVM pass picks between the integer and floating-point forms of an operation by the code around it. This site builds the page’s intrinsics table with that pass turned off, so the table lists PEXTRD for _mm_extract_epi32, where Clang at -O2 printed EXTRACTPS for it in such a function. For the SSE2 baseline both compilers move the element down to position 0 with PSHUFD (GCC uses PUNPCKHDQ for element 2) and copy it with MOVD.

Stores to scattered addresses

The memory form stores an element straight from the vector. For d[i*5] = s[i] * 3 over int arrays, Clang 23 with -march=x86-64-v2 vectorizes the loop and writes each group of four results with one MOVD and three PEXTRDs to addresses 20 bytes apart; GCC 14 keeps the loop scalar.

The same opcode with REX.W is PEXTRQ, for quadwords, in 64-bit mode only. VPEXTRD, the VEX and EVEX form, still reads only an XMM register, and PINSRD goes the other way.

In the optimization guide

What the optimization guide says about PEXTRD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.

Forms

Every encoding of PEXTRD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PEXTRD m32, xmm, imm8` PEXTRD_MEMd_XMMdq_IMMb	`66 0F 3A 16 /r ib`	SSE4.1
`PEXTRD r32, xmm, imm8` PEXTRD_GPR32d_XMMdq_IMMb	`66 0F 3A 16 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: doubleword imm8 of xmm2 goes to m32.

Example: imm8 = 0x02.

With imm8 = 0x02, m32 receives doubleword 2 of xmm2: a2.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.d[imm8 & 3])  # a register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PEXTRD r/m32, xmm, imm8`
`r/m32`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PEXTRD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi32` `int _mm_extract_epi32(__m128i X, const int N)`	`PEXTRD r32, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Element 0 and the others#

Stores to scattered addresses#