PEXTRQ instruction (SSE4.1)

PEXTRQ copies one quadword of an XMM register to a 64-bit general-purpose register or to eight bytes of memory. It is PEXTRD with REX.W, and that page and PEXTRB describe the family: an index fixed in the immediate, and a memory form that writes only its own bytes. Only bit 0 of the immediate counts, and REX.W exists only in 64-bit mode, so 32-bit code has no quadword extract. On Zen 5, pextrq qword ptr [mem], xmm1, 0xcb, with bit 0 set, stored bits 127:64 and left the bytes after them as they were, and pextrq r14, xmm1, 0x4, with bit 0 clear, copied bits 63:0 to R14.

The high half

Element 0 needs no extract: MOVQ copies it, and both compilers use MOVQ for v[0] of a vector of two long longs. For v[1], GCC 14 and Clang 23 at -O2 with -msse4.1 emit pextrq rax, xmm0, 1, and for *p = v[1] the memory form. The SSE2 baseline needs two instructions to reach a register: GCC moves the high half down with MOVHLPS, Clang with PSHUFD, and both finish with MOVQ. To memory, GCC needs only one, MOVHPS, which stores bits 127:64 directly, while Clang shuffles and stores with MOVQ.

Reductions do not use PEXTRQ. For the sum of an array of uint64_t, both compilers add the two halves of the vector inside the register, GCC after PSRLDQ by 8 and Clang after PSHUFD, and move the one result out with MOVQ, even with SSE4.1 enabled.

AMD’s latency spreadsheet for Zen 5 lists PEXTRQ as two macro-ops, on pipes FP0 to FP3 and on FP4 or FP5. PINSRQ goes the other way, and VPEXTRQ, the VEX and EVEX form, still reads only an XMM register: a quadword in the upper half of a YMM register needs VEXTRACTI128 first.

In the optimization guide

What the optimization guide says about PEXTRQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Silvermont to Goldmont Plus

Front end: On Silvermont these instructions come from the microcode ROM; Goldmont decodes them directly, except an indirect call through memory.

Forms

Every encoding of PEXTRQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PEXTRQ m64, xmm, imm8` 64-bit mode only PEXTRQ_MEMq_XMMdq_IMMb	`66 REX.W 0F 3A 16 /r ib`	SSE4.1
`PEXTRQ r64, xmm, imm8` 64-bit mode only PEXTRQ_GPR64q_XMMdq_IMMb	`66 REX.W 0F 3A 16 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: quadword imm8 of xmm2 goes to m64.

Example: imm8 = 0x01.

With imm8 = 0x01, m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.q[imm8 & 1])

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PEXTRQ r/m64, xmm, imm8` 64-bit mode only
`r/m64`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PEXTRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi64` `long long _mm_extract_epi64(__m128i X, const int N)`	`PEXTRQ r64, xmm, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

The high half#