PEXTRW instruction (SSE, SSE2, SSE4.1)

PEXTRW copies one word of a vector register to the low 16 bits of a general-purpose register and clears every bit above it, or, in its SSE4.1 encoding, stores the word to two bytes of memory. It is the oldest of the extracts: the MMX form came with SSE, the XMM form with SSE2, and SSE4.1 added a second opcode, 66 0F 3A 15, with the two operands swapped in the ModRM byte so that the destination can be memory. PEXTRB describes the family: an index fixed in the immediate, and a memory form that writes only its own bytes.

The low two bits of the immediate pick the word of an MMX register, the low three that of an XMM register. On Zen 5, pextrw edx, mm1, 0x29 took word 1, 887Bh, and cleared the rest of RDX, and pextrw word ptr [mem], xmm8, 0x7e stored word 6 and left the bytes after it alone, so bit 3 of the immediate did not count. AMD’s manual names bits 3:0 in its text but bits 2:0 in its table.

The extract of the baseline

As the only extract in SSE2, it serves x86-64 code compiled without -msse4.1 for more than words. In our builds at -O2, GCC 14 and Clang 23 read v[3] of a vector of eight unsigned shorts with pextrw eax, xmm0, 3, and element 0 the same way, since MOVD would bring 32 bits that need clearing again. For a signed short both add CWDE. Clang also reads byte 5 of a byte vector with pextrw eax, xmm0, 2 and a shift right by 8.

With -msse4.1, *p = v[5] becomes the memory form in both compilers instead of an extract and a MOV. For d[i*3] = s[i] + 1 over uint16_t arrays, Clang’s vectorized loop then stores each vector’s eight words with eight memory-form extracts, where the baseline takes a MOVD, seven register extracts and eight MOVs; GCC keeps the loop scalar.

The MMX intrinsic _mm_extract_pi16 compiles to the XMM form in both compilers, as __m64 travels in an XMM register on x86-64; the MMX form would put the x87 unit in MMX state (see EMMS). AMD’s latency spreadsheet for Zen 5 lists two macro-ops for either destination. PINSRW goes the other way, and VPEXTRW is the VEX and EVEX form.

Forms

Every encoding of PEXTRW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PEXTRW r32, mm, imm8` PEXTRW_GPR32_MMXq_IMMb	`NP 0F C5 /r ib`	SSE
`PEXTRW r32, xmm, imm8` PEXTRW_GPR32_XMMdq_IMMb	`66 0F C5 /r ib`	SSE2
`PEXTRW m16, xmm, imm8` PEXTRW_SSE4_MEMw_XMMdq_IMMb	`66 0F 3A 15 /r ib`	SSE4.1
`PEXTRW r32, xmm, imm8` PEXTRW_SSE4_GPR32_XMMdq_IMMb	`66 0F 3A 15 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: word imm8 of xmm2 goes to r32; the upper bits of a register destination are cleared.

Example: imm8 = 0x05.

With imm8 = 0x05, r32 receives word 5 of xmm2: a5.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PEXTRW r32, mm, imm8

dest.write(mm2.w[imm8 & 3])  # zero-extended in a register
# x87: TOP = 0, all tags valid

Run on AMD Zen 5 (EPYC 9645): 1 case.

PEXTRW r32, xmm, imm8 PEXTRW m16, xmm, imm8

dest.write(xmm2.w[imm8 & 7])  # zero-extended in a register

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PEXTRW r32, mm, imm8`
`r32`	explicit	write
`mm`	explicit	read
`imm8`	explicit	read
`PEXTRW r32, xmm, imm8`
`r32`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read
`PEXTRW m16, xmm, imm8`
`m16`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PEXTRW r32, mm, imm8: mmx-nomem
PEXTRW r32, xmm, imm8 PEXTRW m16, xmm, imm8: SSE_TYPE_5

Attributes

What else XED records about the forms. How to read.

PEXTRW r32, mm, imm8: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PEXTRW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi16` `int _mm_extract_epi16(__m128i a, const int imm)`	`PEXTRW r32, xmm, imm8` Legacy -msse2
`_mm_extract_pi16` `int _mm_extract_pi16(__m64 a, const int n)`	`PEXTRW r32, xmm, imm8` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

More SSE4.1 instructions

All 49 SSE4.1 instructions

The extract of the baseline#