Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of PFADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
PFADD mm, m64 PFADD_MMXq_MEMq0F 0F /r 9E3DNow
PFADD mm, mm PFADD_MMXq_MMXq0F 0F /r 9E3DNow

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.
PFADD: element by elementResult single i comes from single i of mm1 and mm2. Result singles 1 to 0: a1+b1, a0+b0.01mm1aa0+b0a1+b1mm101mm2or m64b

Result single i comes from single i of mm1 and mm2. Result singles 1 to 0: a1+b1, a0+b0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

features = cpuid_leaf(0x80000001, 0)[3]
if not features >> 31 & 1:
    fault(UD)                    # CPUID: no 3DNow!
for i in range(2):
    a = mm1.f32[i]
    b = src2.f32[i]
    mm1.f32[i] = add(a, b)
# add: 3DNow!'s sum; a zero term gives the other term as it is,
# +0 + -0 = +0, and an exact 0 takes a's sign (1 + -1 = +0,
# -1 + 1 = -0); exponent 255 is UNDEFINED but beside a zero
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no 3DNow!, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
PFADD mm, mm/m64
mmexplicitread, write
mm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
3DNOW

3DNow
CPUID.80000001H:EDX[31] 3DNow

K10 (Family 10h)

More 3DNow! instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. AMD64 Architecture Programmer's Manual, Volume 5: 64-Bit Media and x87 Floating-Point Instructions (26569, rev. 3.16, November 2021), Wayback Machine copy of AMD's PDF
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.