PHADDD

PHADDD adds neighboring doublewords: every pair of elements in one operand becomes one sum. The destination’s pairs fill the low half of the result and the source’s pairs the high half, so with a in the destination and b in the source, the four doublewords from low to high are a0+a1, a2+a3, b0+b1 and b2+b3. The MMX form does the same with two elements each, giving a0+a1 and b0+b1. The sums wrap at 32 bits and change no flags; only the word version has a saturating sibling, PHADDSW. PHSUBD subtracts the upper element of each pair from the lower one.

In compiled code#

The intrinsic _mm_hadd_epi32(a, b) compiles to PHADDD as written, so two of them on the same register, a tidy way to sum a vector’s four elements, stay two PHADDDs. Left to themselves, compilers do not pick it for that: Clang 23 at -O2 with -mssse3 ends its vectorized integer sums with PSHUFD and PADDD instead. Where they do pick it is a loop whose output elements are sums of input pairs, o[i] = a[2*i] + a[2*i+1]: with -mssse3, Clang 23 loads two vectors and combines them with one PHADDD. GCC 14 does so for pointer arguments with a constant count, but uses two SHUFPS and a PADDD over fixed-size global arrays, and stays scalar for a count known only at run time. Intel’s optimization manual uses the AVX2 form the same way, to add up the products of VPMADDWD in an image transform (Section 15.16, Example 15-38).

Lanes#

VPHADDD, the VEX form, works within each 128-bit lane, so a 256-bit result holds the pairs of a’s low lane, then b’s low lane, then a’s high lane, then b’s high lane. For the pairs loop with -mavx2, Clang 23 follows each VPHADDD with VPERMQ 0xD8 to put the sums back in order, while GCC 14 gathers the even and the odd elements with VPERMD and VPBLENDD and adds them with one VPADDD. AVX-512 has no horizontal adds, so there is no EVEX form.

The SSSE3 form with a memory operand needs it aligned to 16 bytes. HADDPS is the instruction for singles.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(2):
    j = 2 * (i % 1)
    if i < 1:
        mm1.d[i] = src1.d[j] + src1.d[j + 1]
    else:
        mm1.d[i] = src2.d[j] + src2.d[j + 1]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        a = src1.d[j]
        b = src1.d[j + 1]
        xmm1.d[i] = a + b
    else:
        a = src2.d[j]
        b = src2.d[j + 1]
        xmm1.d[i] = a + b
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PHADDD mm, mm/m64

mmx-mem

PHADDD xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PHADDD mm, mm/m64

may abort a TSX transaction

PHADDD xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHADDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW