PHADDSW

PHADDSW adds neighboring pairs of signed words and clamps each sum to the range of a word, -32768 to 32767, where PHADDW lets it wrap. The pairs are laid out as PHADDD describes for doublewords: the destination’s sums fill the low half of the result and the source’s the high half, so phaddsw xmm0, xmm1 gives the four sums of XMM0’s pairs below the four of XMM1’s, and the MMX form two and two. No flag reports a clamped sum. PHSUBSW is the subtracting twin; SSSE3 has no saturating horizontal add for bytes or doublewords.

On Zen 5, the recorded phaddsw xmm7, xmm11, and its memory form given the same values, turned the pair 8000h, 8000h (-65536) into 8000h and the pair FFFFh, 8000h (-32769) into 8000h, where PHADDW would have returned 0000h and 7FFFh; the pair FFFFh, 7FFFh gave 7FFEh, which needs no clamping. Both left bits 511:128 of XMM7 as they were, as legacy SSE instructions do (see mixing SSE and AVX).

In compiled code#

In our builds at -O2 over fixed-size int16_t arrays, Clang 23 recognizes a clamped sum of adjacent elements, o[i] = sat16(a[2*i] + a[2*i+1]) with sat16 clamping an int to the word range, and compiles it to one PHADDSW per eight results with -mssse3; with -mavx2 it uses VPHADDSW, which works within each 128-bit lane, and puts the results back in order with VPERMQ. GCC 14 does not pick the instruction from C: it separates the even and odd words with PSHUFB, widens them to doublewords, adds, and clamps with compares and masks, about fifty instructions per eight results (PMAXSD and PMINSD do the clamping with -march=x86-64-v2). Both compile the intrinsic _mm_hadds_epi16 to PHADDSW.

AMD’s latency spreadsheet for Zen 5 gives PHADDSW four macro-ops with a latency of three cycles and one started every two cycles; PHADDW takes two cycles, and the vertical PADDSW is one macro-op of two cycles, two per cycle. The XMM form’s memory operand must be aligned to 16 bytes; SSSE3 is part of x86-64-v2.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        sa = src1.sw[j]
        sb = src1.sw[j + 1]
        mm1.w[i] = ssat(sa + sb, 16)
    else:
        sa = src2.sw[j]
        sb = src2.sw[j + 1]
        mm1.w[i] = ssat(sa + sb, 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = 2 * (i % 4)
    if i < 4:
        sa = src1.sw[j]
        sb = src1.sw[j + 1]
        xmm1.w[i] = ssat(sa + sb, 16)
    else:
        sa = src2.sw[j]
        sb = src2.sw[j + 1]
        xmm1.w[i] = ssat(sa + sb, 16)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PHADDSW mm, mm/m64

mmx-mem

PHADDSW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PHADDSW mm, mm/m64

may abort a TSX transaction

PHADDSW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHADDSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW