PHMINPOSUW instruction (SSE4.1)

PHMINPOSUW finds the smallest of the eight unsigned words of its source and returns it in word 0 of the destination, with its index, 0 to 7, in word 1; words 2 to 7 are cleared. When several words share the minimum, the lowest index wins: in the cases recorded on Zen 5, a source with zeros in words 2, 4 and 7 gave index 2, and one with zeros in words 4 and 7 gave 4. It is the only horizontal minimum in SSE, AVX and AVX-512, and it has no wider form: VPHMINPOSUW is the VEX encoding of the same 128-bit operation, which clears the register above bit 127, and neither AVX2 nor AVX-512 adds a 256- or 512-bit version.

The end of a reduction

Compilers use it for the last step of a vectorized minimum. Clang 23 at -O2 with -march=x86-64-v2 keeps running minimums with PMINUW over the array, then reduces the last vector with one PHMINPOSUW and reads word 0 with MOVD. It bends other reductions to fit:

Unsigned maximum: the words are inverted with PXOR against all ones, so the largest becomes the smallest, and the result is inverted back with NOT.
Signed minimum: XOR with 8000h maps signed order onto unsigned order, and the same XOR undoes it.
Unsigned bytes: PSRLW by 8 and PMINUB leave in each word the smaller of its two bytes, with a zero upper byte, and PHMINPOSUW finishes.

GCC 14 at -O2 uses PHMINPOSUW for the same unsigned minimum when the trip count is a constant, after a loop of PMINUW, but keeps these loops scalar when the count is a variable. Neither compiler uses the index: a C loop that tracks the position of the minimum stays scalar.

With MPSADBW

Intel’s optimization manual pairs it with MPSADBW for motion estimation (Section 6.6.10): MPSADBW computes the sums of absolute differences of a block at eight positions as eight words, and PHMINPOSUW returns the best match and its position in one step. AMD’s Zen 5 guide lists PHMINPOSUW as one macro-op with a latency of 3 cycles.

The legacy form keeps bits 128 and up of the destination and needs a memory operand aligned to 16 bytes.

Forms

Every encoding of PHMINPOSUW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PHMINPOSUW xmm, m128` PHMINPOSUW_XMMdq_MEMdq	`66 0F 38 41 /r`	SSE4.1
`PHMINPOSUW xmm, xmm` PHMINPOSUW_XMMdq_XMMdq	`66 0F 38 41 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The smallest unsigned word goes to word 0 of the result, its index to word 1 (the lowest index if several are equal), and the other words are cleared.

Result words 0 and 1 depend on all eight words of the source; words 7 to 2 are 0. Result words 7 to 0: 0, 0, 0, 0, 0, 0, index, min.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

m = src2.w[0]
x = 0
for i in range(1, 8):
    if src2.w[i] < m:    # the first of equal words stays
        m = src2.w[i]
        x = i
xmm1.write(x << 16 | m)  # words 7 to 2 are zeroed
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PHMINPOSUW xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHMINPOSUW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_minpos_epu16` `__m128i _mm_minpos_epu16(__m128i __V)`	`PHMINPOSUW xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

The end of a reduction#

With MPSADBW#