PHSUBD

PHSUBD subtracts within neighboring pairs of doublewords, the upper element of each pair from the lower one, with the destination’s differences in the low half of the result and the source’s in the high half: a0-a1, a2-a3, b0-b1, b2-b3 for an XMM register, a0-a1 and b0-b1 for an MMX one. PHADDD is the adding form and explains the layout. The differences wrap at 32 bits, set no flag, and there is no saturating doubleword form. Zen 5’s recorded cases:

• phsubd xmm7, xmm11 turned 7FFFFFFFh minus 80000000h into FFFFFFFFh and FFFFFFFFh minus 80000000h into 7FFFFFFFh, and kept bits 511:128 of XMM7 (see mixing SSE and AVX);
• phsubd mm3, mm3, with the same register as both operands, gave FFFFFFFFh (0 - 1) in both halves, the low result from the destination and the high one from the source.

In compiled code#

In our builds at -O2 over fixed-size int32_t arrays, the loop o[i] = a[2*i] - a[2*i+1] compiles to PHSUBD with -mssse3 in both GCC 14 and Clang 23, each loading one vector and subtracting the next straight from memory. GCC treats the sum differently: the same loop with a plus becomes two SHUFPS and a PADDD rather than PHADDD. With -mavx2, Clang uses VPHSUBD, which works within each 128-bit lane, and reorders the result with VPERMQ, while GCC gathers the even and odd elements with VPERMD and VPBLENDD before one VPSUBD. The intrinsic _mm_hsub_epi32 is PHSUBD in both, even with the same register twice.

AMD’s latency spreadsheet for Zen 5 gives PHSUBD four macro-ops with a latency of two cycles and one started every two cycles; SSSE3 added it with an MMX and an XMM form, the latter’s memory operand aligned to 16 bytes.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(2):
    j = 2 * (i % 1)
    if i < 1:
        mm1.d[i] = src1.d[j] - src1.d[j + 1]
    else:
        mm1.d[i] = src2.d[j] - src2.d[j + 1]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        a = src1.d[j]
        b = src1.d[j + 1]
        xmm1.d[i] = a - b
    else:
        a = src2.d[j]
        b = src2.d[j + 1]
        xmm1.d[i] = a - b
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PHSUBD mm, mm/m64

mmx-mem

PHSUBD xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PHSUBD mm, mm/m64

may abort a TSX transaction

PHSUBD xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHSUBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW