PHSUBSW

PHSUBSW subtracts the upper word of each neighboring pair from the lower one and clamps the difference to the word range, -32768 to 32767, in the layout of the other horizontal operations: the destination’s pairs give the low half of the result, the source’s the high half. PHADDSW is the adding form and covers what compilers do with the pair, and PHSUBW the wrapping one. No flag reports a clamped difference.

On Zen 5, the recorded phsubsw xmm1, xmm2 turned the pair 8000h, 7FFFh into 8000h, clamping -65535, and 8000h, 0001h into 8000h, clamping -32769, and gave FFF1h for 0000h, 000Fh; it left bits 511:128 of XMM1 as they were (see mixing SSE and AVX). In phsubsw mm1, mm2, the pair FFFFh, 7FFFh gave 8000h exactly: -1 - 32767 is -32768, inside the range, so the same result comes from PHSUBW too. A positive overflow, such as 0 minus 8000h, clamps to 7FFFh.

In compiled code#

As for PHADDSW, in our builds at -O2 over fixed-size int16_t arrays Clang 23 turns the clamped difference of adjacent elements into one PHSUBSW per eight results with -mssse3 (and VPHSUBSW with a VPERMQ with -mavx2), while GCC 14 widens the words to doublewords, subtracts and clamps; both compile _mm_hsubs_epi16 to the instruction.

AMD’s latency spreadsheet for Zen 5 gives PHSUBSW four macro-ops with a latency of three cycles and one started every two cycles, against one macro-op, two cycles and two per cycle for the vertical PSUBSW. The XMM form’s memory operand must be aligned to 16 bytes.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        sa = src1.sw[j]
        sb = src1.sw[j + 1]
        mm1.w[i] = ssat(sa - sb, 16)
    else:
        sa = src2.sw[j]
        sb = src2.sw[j + 1]
        mm1.w[i] = ssat(sa - sb, 16)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = 2 * (i % 4)
    if i < 4:
        sa = src1.sw[j]
        sb = src1.sw[j + 1]
        xmm1.w[i] = ssat(sa - sb, 16)
    else:
        sa = src2.sw[j]
        sb = src2.sw[j + 1]
        xmm1.w[i] = ssat(sa - sb, 16)
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PHSUBSW mm, mm/m64

mmx-mem

PHSUBSW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PHSUBSW mm, mm/m64

may abort a TSX transaction

PHSUBSW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHSUBSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW