PHSUBW

PHSUBW subtracts within neighboring pairs of words, the upper word of each pair from the lower one, and keeps the low 16 bits of each difference: the destination’s pairs fill the low half of the result and the source’s the high half, as PHADDW lays out its sums. Nothing saturates and no flag is set; PHSUBSW is the clamping form. The recorded Zen 5 case phsubw xmm7, xmmword ptr [mem] shows both the order and the wrap: the pair 000Fh, 0010h gave FFFFh (15 - 16), and 7FFFh, 8000h also gave FFFFh, the low bits of 32767 - (-32768) = 65535, where PHSUBSW would have returned 7FFFh. In the memory half, FFFFh, 8000h gave 7FFFh. Bits 511:128 of XMM7 stayed as they were (see mixing SSE and AVX).

In compiled code#

In our builds at -O2 over fixed-size int16_t arrays, Clang 23 compiles o[i] = a[2*i] - a[2*i+1] to one PHSUBW per eight results with -mssse3, and to VPHSUBW and a VPERMQ that puts the 128-bit lanes in order with -mavx2. GCC 14 separates the even and odd words, with PSHUFB and POR or with masks, shifts and PACKUSDW, and subtracts them with PSUBW, as it does for the sums. The intrinsic _mm_hsub_epi16 is PHSUBW in both.

AMD’s latency spreadsheet for Zen 5 gives PHSUBW, like PHADDW, four macro-ops with a latency of two cycles and one started every two cycles. The MMX form came with SSSE3 too, and the XMM form’s memory operand must be aligned to 16 bytes.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

src1 = mm1.read()  # mm1 as it was
for i in range(4):
    j = 2 * (i % 2)
    if i < 2:
        mm1.w[i] = src1.w[j] - src1.w[j + 1]
    else:
        mm1.w[i] = src2.w[j] - src2.w[j + 1]
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

src1 = xmm1.read()  # xmm1 as it was
for i in range(8):
    j = 2 * (i % 4)
    if i < 4:
        a = src1.w[j]
        b = src1.w[j + 1]
        xmm1.w[i] = a - b
    else:
        a = src2.w[j]
        b = src2.w[j + 1]
        xmm1.w[i] = a - b
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PHSUBW mm, mm/m64

mmx-mem

PHSUBW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PHSUBW mm, mm/m64

may abort a TSX transaction

PHSUBW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PHSUBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PMADDUBSW
• PMULHRSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW