PINSRD instruction (SSE4.1)

PINSRD writes a doubleword from a general-purpose register or from memory into one element of an XMM register and leaves the other three as they were. The low two bits of the immediate choose the element, and the rest of the immediate is ignored. Since the old contents are kept, the destination is an input too: PINSRD has to wait for whatever last wrote that register.

Building vectors

Inserting one element compiles to one PINSRD once SSE4.1 is enabled: for x[2] = a on a vector of four ints, GCC 14 and Clang 23 at -O2 both emit pinsrd xmm0, edi, 2. For the SSE2 baseline, which has no doubleword insert, GCC moves the element into place with two PSHUFDs around a MOVSS and Clang with two SHUFPSs.

Building a whole vector from four registers, _mm_setr_epi32(a, b, c, d), shows two styles. Clang 23 starts with MOVD and inserts the other three with PINSRD, one after another. GCC 14 builds two halves side by side, each a MOVD and a PINSRD, and joins them with PUNPCKLQDQ, so that the two PINSRDs do not depend on each other. Without SSE4.1 both use MOVDs and unpacks only.

The memory form loads exactly four bytes, with no alignment requirement, so it can gather elements that are not next to each other: Intel’s optimization manual loads four doublewords from a strided array with one MOVD and three PINSRDs (Section 6.4.8).

Other sizes and encodings

PINSRQ is the same opcode with REX.W, for quadwords, in 64-bit mode only. PINSRB inserts bytes, and PINSRW, which came long before SSE4.1, words.
The legacy form leaves bits 128 and up of the YMM or ZMM register unchanged.
VPINSRD, the VEX and EVEX form, takes the other three elements from a separate source register, so the destination can be a new register, and clears everything above bit 127.

For single-precision values, INSERTPS inserts from another XMM register and can also zero chosen elements. PEXTRD is the reverse operation.

Forms

Every encoding of PINSRD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PINSRD xmm, m32, imm8` PINSRD_XMMdq_MEMd_IMMb	`66 0F 3A 22 /r ib`	SSE4.1
`PINSRD xmm, r32, imm8` PINSRD_XMMdq_GPR32d_IMMb	`66 0F 3A 22 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: the doubleword from r32 replaces doubleword imm8 of xmm1; the rest of the result comes from xmm1.

Example: imm8 = 0x02.

With imm8 = 0x02, result doublewords 3 to 0: a3, b0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.d[imm8 & 3] = src2.d[0]  # the others keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PINSRD xmm, r/m32, imm8`
`xmm`	explicit	read, write
`r/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PINSRD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_epi32` `__m128i _mm_insert_epi32(__m128i X, int I, const int N)`	`PINSRD xmm, r32, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Building vectors#

Other sizes and encodings#