PINSRQ instruction (SSE4.1)

PINSRQ writes a quadword from a 64-bit general-purpose register or from memory into one half of an XMM register and keeps the other half. It is PINSRD with REX.W; that page describes the family: the destination is also an input, the memory form reads exactly its own bytes at any alignment, and the legacy form leaves bits 128 and up alone. Only bit 0 of the immediate counts. REX.W exists only in 64-bit mode, so 32-bit code has no quadword insert.

On Zen 5, pinsrq xmm12, qword ptr [mem], 0x57, with bit 0 set, replaced bits 127:64 with the eight bytes from memory, and pinsrq xmm12, rdx, 0x6e, with bit 0 clear, replaced bits 63:0 with RDX; in both, bits 511:128 of ZMM12 kept their values.

Two 64-bit values

Building a vector from two long longs, (v2di){a, b} with GCC’s vector_size(16) type, shows two styles at -O2 with -march=x86-64-v2. GCC 14 moves a in with MOVQ and inserts b with pinsrq xmm0, rsi, 1. Clang 23 moves both with MOVQ and joins them with PUNPCKLQDQ, so that neither move waits for the other; for the SSE2 baseline both compilers do that.

Replacing one half of an existing vector, v[1] = x or v[0] = x, is a single PINSRQ in both compilers at x86-64-v2, from a register or from memory. The baseline needs other instructions for each case: for the high half, MOVQ and PUNPCKLQDQ in both; for the low half, Clang uses MOVQ and MOVSD and GCC saves the high half with MOVHLPS first; and for a high half loaded from memory, GCC uses one MOVHPS and Clang a MOVSD load and MOVLHPS.

PEXTRQ reads a quadword out, and VPINSRQ, the VEX and EVEX form, takes the kept half from a separate source register and clears bits 128 and up.

Forms

Every encoding of PINSRQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PINSRQ xmm, m64, imm8` 64-bit mode only PINSRQ_XMMdq_MEMq_IMMb	`66 REX.W 0F 3A 22 /r ib`	SSE4.1
`PINSRQ xmm, r64, imm8` 64-bit mode only PINSRQ_XMMdq_GPR64q_IMMb	`66 REX.W 0F 3A 22 /r ib`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: the quadword from r64 replaces quadword imm8 of xmm1; the rest of the result comes from xmm1.

Example: imm8 = 0x01.

With imm8 = 0x01, result quadwords 1 to 0: b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.q[imm8 & 1] = src2.q[0]  # the others keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PINSRQ xmm, r/m64, imm8` 64-bit mode only
`xmm`	explicit	read, write
`r/m64`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PINSRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_epi64` `__m128i _mm_insert_epi64(__m128i X, long long I, const int N)`	`PINSRQ xmm, r64, imm8` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Two 64-bit values#