PINSRW instruction (SSE, SSE2)

PINSRW writes the low word of a 32-bit general-purpose register, or a word of memory, into one element of an MMX or XMM register and keeps the others. It came with SSE for MMX registers and with SSE2 for XMM ones, long before SSE4.1’s PINSRB and PINSRD, whose page describes what the inserts share: the destination is also an input, and the memory form reads only its own bytes, at any address. The low two bits of the immediate pick the word of an MMX register, the low three that of an XMM register. On Zen 5, pinsrw xmm0, word ptr [mem], 0xd6 put 00C5h into word 6, pinsrw xmm4, r9d, 0x53 put B9DFh, the low word of R9, into word 3, and pinsrw mm7, word ptr [mem], 0x4 wrote word 0, its bit 2 ignored. The XMM cases left bits 511:128 of their registers alone.

Building vectors of words

In our builds at -O2 for the x86-64 baseline, GCC 14 and Clang 23 compile v[3] = x on a vector of eight shorts to pinsrw xmm0, edi, 3, and to the memory form when x comes from a pointer. Building a whole vector, _mm_setr_epi16(a, b, ... h), shows two styles:

GCC starts four pairs with MOVD, inserts the second word of each, and joins the pairs with PUNPCKLDQ and PUNPCKLQDQ, so that no insert waits for another.
Clang inserts nothing for the baseline and pairs the words with PUNPCKLWD. With -msse4.1 it switches to one MOVD and a chain of seven inserts, each waiting for the last, also for eight words loaded from scattered addresses.

Intel’s optimization manual recommends zeroing an MMX register with PXOR, or loading it, before a series of inserts that replaces all its words, so that the first insert does not depend on the old contents (Section 6.4.7).

The MMX intrinsic _mm_insert_pi16 compiles to the XMM form in both compilers on x86-64. AMD’s latency spreadsheet for Zen 5 lists the register form as two macro-ops and the memory form as one. PEXTRW reads a word out, and VPINSRW, the VEX and EVEX form, takes the other words from a separate source register and clears bits 128 and up.

Forms

Every encoding of PINSRW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PINSRW mm, m16, imm8` PINSRW_MMXq_MEMw_IMMb	`NP 0F C4 /r ib`	SSE
`PINSRW mm, r32, imm8` PINSRW_MMXq_GPR32_IMMb	`NP 0F C4 /r ib`	SSE
`PINSRW xmm, m16, imm8` PINSRW_XMMdq_MEMw_IMMb	`66 0F C4 /r ib`	SSE2
`PINSRW xmm, r32, imm8` PINSRW_XMMdq_GPR32_IMMb	`66 0F C4 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: the word from r32 replaces word imm8 of xmm1; the rest of the result comes from xmm1.

Example: imm8 = 0x05.

With imm8 = 0x05, result words 7 to 0: a7, a6, b0, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PINSRW mm, m16, imm8 PINSRW mm, r32, imm8

mm1.w[imm8 & 3] = src2.w[0]  # the others keep their values
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PINSRW xmm, m16, imm8 PINSRW xmm, r32, imm8

xmm1.w[imm8 & 7] = src2.w[0]  # the others keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PINSRW mm, m16, imm8`
`mm`	explicit	read, write
`m16`	explicit	read
`imm8`	explicit	read
`PINSRW mm, r32, imm8`
`mm`	explicit	read, write
`r32`	explicit	read
`imm8`	explicit	read
`PINSRW xmm, m16, imm8`
`xmm`	explicit	read, write
`m16`	explicit	read
`imm8`	explicit	read
`PINSRW xmm, r32, imm8`
`xmm`	explicit	read, write
`r32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PINSRW mm, m16, imm8 PINSRW mm, r32, imm8: mmx-mem
PINSRW xmm, m16, imm8 PINSRW xmm, r32, imm8: SSE_TYPE_5

Attributes

What else XED records about the forms. How to read.

PINSRW mm, m16, imm8 PINSRW mm, r32, imm8: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PINSRW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_epi16` `__m128i _mm_insert_epi16(__m128i a, int b, const int imm)`	`PINSRW xmm, r32, imm8` Legacy -msse2
`_mm_insert_pi16` `__m64 _mm_insert_pi16(__m64 a, int d, const int n)`	`PINSRW xmm, r32, imm8` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

Building vectors of words#