PMADDWD instruction (MMX, SSE2)

PMADDWD multiplies signed words pairwise into full 32-bit products and adds each even product to the odd one next to it, so a 128-bit register of eight words becomes four doublewords, each of the form a0*b0 + a1*b1. It is the instruction for dot products of 16-bit data: audio samples, fixed-point filter taps, the coefficients of image and video transforms.

The one overflow

No product of two words is larger than 1,073,741,824 in magnitude, so the sum of two fits a signed doubleword in every case but one: when all four words are 8000h (-32768), the sum is 2,147,483,648, one more than the largest signed doubleword, and it wraps to 80000000h, a negative number. Nothing saturates and no flag reports it. Code that cannot rule this input out keeps one of its operands away from -32768.

In compiled code

GCC 14 at -O2 compiles s += a[i] * b[i] over int16_t arrays to a loop of PMADDWD and PADDD, with the products of each pair already added; only the four partial sums need adding at the end. Clang 23 does the same with -mavx2, but for the SSE2 baseline and with -msse4.1 it first spreads the words out with a zero next to each, so every doubleword holds one product, four per instruction instead of eight. With a vector of ones as the other operand, PMADDWD adds neighboring signed words into doublewords, which cannot overflow.

Intel’s optimization manual builds a complex multiplication from it: with the coefficient stored as the words Cr, -Ci, Ci, Cr and the value duplicated, one PMADDWD gives the real and the imaginary part (Section 6.6.12).

Its relatives

For byte data, PMADDUBSW multiplies unsigned bytes by signed ones into saturated word sums, and PMADDWD with ones then widens those to doublewords. The VNNI instructions fold such chains into one: VPDPWSSD is PMADDWD plus the accumulating addition, and VPDPBUSD replaces the three-step byte version; Intel’s optimization manual notes that the fused instruction is also more accurate, since it does not saturate a 16-bit middle step (Section 8.2.1). VPMADDWD is the VEX and EVEX form; the legacy SSE2 form needs a memory operand aligned to 16 bytes.

Forms

Every encoding of PMADDWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMADDWD mm, m64` PMADDWD_MMXq_MEMq	`NP 0F F5 /r`	MMX
`PMADDWD mm, mm` PMADDWD_MMXq_MMXq	`NP 0F F5 /r`	MMX
`PMADDWD xmm, m128` PMADDWD_XMMdq_MEMdq	`66 0F F5 /r`	SSE2
`PMADDWD xmm, xmm` PMADDWD_XMMdq_XMMdq	`66 0F F5 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Groups of 2 adjacent words are combined into one doubleword.

Result doubleword i comes from words 2i to 2i+1 of xmm1 and xmm2. Result doublewords 3 to 0: sum, sum, sum, sum.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMADDWD mm, mm/m64

for i in range(2):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += mm1.sw[j] * src2.sw[j]
    mm1.d[i] = x
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMADDWD xmm, xmm/m128

for i in range(4):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += xmm1.sw[j] * src2.sw[j]
    xmm1.d[i] = x
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMADDWD mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMADDWD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMADDWD mm, mm/m64: mmx-mem
PMADDWD xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMADDWD mm, mm/m64: may abort a TSX transaction
PMADDWD xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMADDWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_madd_epi16` `__m128i _mm_madd_epi16(__m128i __a, __m128i __b)`	`PMADDWD xmm, xmm` Legacy -msse2
`_mm_madd_pi16` `__m64 _mm_madd_pi16(__m64 __m1, __m64 __m2)`	`PMADDWD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`PENTIUMMMX` MMX	MMX `CPUID.01H:EDX[23]` MMX	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More MMX instructions

All 47 MMX instructions

More SSE2 instructions

All 124 SSE2 instructions

The one overflow#

In compiled code#

Its relatives#