PMAXSB instruction (SSE4.1)

PMAXSB keeps the larger of each pair of bytes, compared as signed integers, 16 results in an XMM register. There is no MMX form. On Zen 5, the recorded pmaxsb xmm1, xmm2 kept 01h over FFh (1 over -1), FFh over 80h (-1 over -128) and 7Fh over FFh, where the unsigned PMAXUB would have kept FFh each time, and left bits 255:128 of the register as they were (see mixing SSE and AVX). PMINSB is its partner.

SSE4.1, not SSE2

SSE2 has only two byte and word maxima, PMAXUB for unsigned bytes and PMAXSW for signed words; PMAXSB came with SSE4.1, with PMINSB, the unsigned word and the doubleword forms. SSE4.1 is part of x86-64-v2, so code built for the baseline does without it. In our builds at -O2 over int8_t arrays:

Maximum. b[i] > c[i] ? b[i] : c[i] is one PMAXSB per 16 bytes with -march=x86-64-v2 in GCC 14 and Clang 23. For the baseline, both compare with PCMPGTB and select with PAND, PANDN and POR: four instructions instead of one.
ReLU. b[i] > 0 ? b[i] : 0 is PMAXSB against a zeroed register at -v2, and PCMPGTB against zero with a PAND for the baseline.
Clamping. Limiting bytes to -100..100 is a PMAXSB and a PMINSB against constant vectors at -v2, GCC taking the minimum first and Clang the maximum; the baseline needs two compares and two selects.
Largest element. At -v2 GCC folds each block into a register with PMAXSB and halves the register four times, shifting it with PSRLDQ. Clang flips the order with a PXOR against 7Fh, so that the signed maximum becomes an unsigned minimum, folds byte pairs into words with PSRLW and PMINUB, and lets PHMINPOSUW finish.

The legacy form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives it one cycle, four per cycle. VPMAXSB is the VEX and EVEX form.

Forms

Every encoding of PMAXSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMAXSB xmm, m128` PMAXSB_XMMdq_MEMdq	`66 0F 38 3C /r`	SSE4.1
`PMAXSB xmm, xmm` PMAXSB_XMMdq_XMMdq	`66 0F 38 3C /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 16 bytes in the xmm form.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    xmm1.b[i] = max(xmm1.sb[i], src2.sb[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMAXSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMAXSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_epi8` `__m128i _mm_max_epi8(__m128i __V1, __m128i __V2)`	`PMAXSB xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

SSE4.1, not SSE2#