PMAXSD instruction (SSE4.1)

PMAXSD keeps the larger of each pair of doublewords, compared as signed integers, 4 results in an XMM register. There is no MMX form. On Zen 5, the recorded pmaxsd xmm7, xmm11 kept 00000001h over 80000000h (1 over -2147483648) and FFFFFFFFh over 80000000h (-1 over -2147483648), where the unsigned PMAXUD would have kept 80000000h both times, and left bits 255:128 of the register as they were (see mixing SSE and AVX). PMINSD is its partner.

SSE4.1, not SSE2

SSE2 has only a signed word maximum, PMAXSW, and an unsigned byte one, PMAXUB; PMAXSD came with SSE4.1, along with PMINSD and the unsigned doubleword forms, part of x86-64-v2. PMAXSB covers what the signed family shares (the compare-and-select the baseline needs instead, ReLU and clamping) across element sizes; this page gives only what differs for doublewords. In our builds at -O2 over int32_t arrays:

Maximum. b[i] > c[i] ? b[i] : c[i] is one PMAXSD per 4 doublewords with -march=x86-64-v2 in GCC 14 and Clang 23. For the baseline, both compare with PCMPGTD and select with PAND, PANDN and POR: four instructions instead of one.
ReLU. b[i] > 0 ? b[i] : 0 is PMAXSD against a zeroed register at -v2, and PCMPGTD against zero with a PAND for the baseline, the pattern Intel’s optimization manual shows with the EVEX form in a quantized matrix-multiply example.
Clamping. Limiting int32_t values to a lower and an upper bound takes one PMAXSD and one PMINSD against constant vectors at -v2; the baseline needs a compare and a select for each bound.

The legacy form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives it one cycle, four per cycle. VPMAXSD is the VEX and EVEX form, the latter with masking and a broadcast doubleword.

Forms

Every encoding of PMAXSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMAXSD xmm, m128` PMAXSD_XMMdq_MEMdq	`66 0F 38 3D /r`	SSE4.1
`PMAXSD xmm, xmm` PMAXSD_XMMdq_XMMdq	`66 0F 38 3D /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = max(xmm1.sd[i], src2.sd[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMAXSD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMAXSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_epi32` `__m128i _mm_max_epi32(__m128i __V1, __m128i __V2)`	`PMAXSD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

SSE4.1, not SSE2#