PMAXSW instruction (SSE, SSE2)

PMAXSW keeps the larger of each pair of words, compared as signed 16-bit integers: 8 results in an XMM register, 4 in an MMX register. On Zen 5, the recorded pmaxsw xmm8, xmm15 kept 7FFFh over 8000h and 0001h over FFFFh (1 over -1), where an unsigned maximum would have kept 8000h and FFFFh, and left bits 255:128 of the register as they were (see mixing SSE and AVX). Its partner PMINSW covers what the pair shares: clamping to a range with one of each, the reductions, absolute values as the maximum of x and 0 - x, and why words are the only signed elements SSE2 can take the minimum or maximum of.

In compiled code

In our builds at -O2 for the x86-64 baseline, over arrays of 1024 words:

Maximum and ReLU. s[i] > t[i] ? s[i] : t[i] over int16_t is one PMAXSW per 8 words, and s[i] > 0 ? s[i] : 0, which clears the negative elements, is a PMAXSW against a zeroed register in GCC 14 and Clang 23.
Largest element. GCC 14 starts from 8000h in every word, folds each block into it, halves the register with PSRLDQ by 8, 4 and 2, and reads word 0 with PEXTRW. Clang 23 keeps two running maxima and finishes with PSHUFD and PSRLD.
Unsigned words. PMAXUW came with SSE4.1, so the baseline needs a detour for uint16_t: both compilers take t + sat(s - t), a PSUBUSW and a PADDW, as the saturated difference is zero where t is the greater and s - t elsewhere. With -march=x86-64-v2 it is one PMAXUW.

AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle on pipes FP0 to FP3. The MMX form came with SSE rather than MMX, the XMM form with SSE2, and the legacy XMM form needs a memory operand aligned to 16 bytes. VPMAXSW is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about PMAXSW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

Vectors on all parts: Many MMX instructions, among them the saturating additions and subtractions, comparisons, pmaxsw, pminsw, pavgb and pabsb, run on one port at half Broadwell’s rate.

Forms

Every encoding of PMAXSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMAXSW mm, m64` PMAXSW_MMXq_MEMq	`NP 0F EE /r`	SSE
`PMAXSW mm, mm` PMAXSW_MMXq_MMXq	`NP 0F EE /r`	SSE
`PMAXSW xmm, m128` PMAXSW_XMMdq_MEMdq	`66 0F EE /r`	SSE2
`PMAXSW xmm, xmm` PMAXSW_XMMdq_XMMdq	`66 0F EE /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMAXSW mm, mm/m64

for i in range(4):
    mm1.w[i] = max(mm1.sw[i], src2.sw[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMAXSW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = max(xmm1.sw[i], src2.sw[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMAXSW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMAXSW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMAXSW mm, mm/m64: mmx-mem
PMAXSW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMAXSW mm, mm/m64: may abort a TSX transaction
PMAXSW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMAXSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_epi16` `__m128i _mm_max_epi16(__m128i __a, __m128i __b)`	`PMAXSW xmm, xmm` Legacy -msse2
`_mm_max_pi16` `__m64 _mm_max_pi16(__m64 __a, __m64 __b)`	`PMAXSW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#