PMAXUB instruction (SSE, SSE2)

PMAXUB keeps the larger of each pair of bytes, compared as unsigned numbers: 16 results in an XMM register, 8 in an MMX register. On Zen 5, the recorded pmaxub xmm8, xmm15 chose 80h over 7Fh and FFh over 01h, where a signed maximum would have kept 7Fh and 01h, and left bits 255:128 of the register as they were, as legacy SSE instructions do (see mixing SSE and AVX).

It is the partner of PMINUB, whose page covers what the pair shares: SSE2 has only the unsigned byte and signed word forms of the minimum and maximum, clamping to a range with one of each, and unsigned compares built from them. The maximum adds its own uses, here from GCC 14 and Clang 23 at -O2 for the SSE2 baseline:

Maximum loops. a[i] = b[i] > c[i] ? b[i] : c[i] over uint8_t is one PMAXUB per 16 bytes. Over int8_t it is not: the signed PMAXSB came with SSE4.1, and the baseline needs PCMPGTB and a select.
Reductions. For the largest byte of an array, GCC folds each block into one register with PMAXUB, then halves the register four times with PSRLDQ by 8, 4, 2 and 1 and a PMAXUB after each. Clang does the same with PSHUFD and shifts. With -march=x86-64-v2, Clang inverts the bytes, folds each pair into a word with PSRLW and PMINUB, and finishes with PHMINPOSUW, SSE4.1’s horizontal minimum of words.
Unsigned greater or equal. b[i] >= c[i] holds exactly where the maximum of the two is b[i]: Clang compiles it to PMAXUB and PCMPEQB, GCC to the mirror image with PMINUB.
Absolute differences. b[i] > c[i] ? b[i] - c[i] : c[i] - b[i] is PMAXUB minus PMINUB in Clang, a subtraction with PSUBB that cannot underflow; GCC selects between the two differences instead. For sums of them, PSADBW does the whole job.

Intel’s optimization manual counts the MMX form among those that Skylake runs at half the throughput of earlier cores (Section 15.16.5). AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. The MMX form came with SSE, the XMM form with SSE2, and the legacy XMM form needs a memory operand aligned to 16 bytes. VPMAXUB is the VEX and EVEX form.

Forms

Every encoding of PMAXUB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMAXUB mm, m64` PMAXUB_MMXq_MEMq	`NP 0F DE /r`	SSE
`PMAXUB mm, mm` PMAXUB_MMXq_MMXq	`NP 0F DE /r`	SSE
`PMAXUB xmm, m128` PMAXUB_XMMdq_MEMdq	`66 0F DE /r`	SSE2
`PMAXUB xmm, xmm` PMAXUB_XMMdq_XMMdq	`66 0F DE /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMAXUB mm, mm/m64

for i in range(8):
    mm1.b[i] = max(mm1.b[i], src2.b[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMAXUB xmm, xmm/m128

for i in range(16):
    xmm1.b[i] = max(xmm1.b[i], src2.b[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMAXUB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMAXUB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMAXUB mm, m64: mmx-mem
PMAXUB mm, mm: none in XED
PMAXUB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMAXUB mm, mm/m64: may abort a TSX transaction
PMAXUB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMAXUB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_epu8` `__m128i _mm_max_epu8(__m128i __a, __m128i __b)`	`PMAXUB xmm, xmm` Legacy -msse2
`_mm_max_pu8` `__m64 _mm_max_pu8(__m64 __a, __m64 __b)`	`PMAXUB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions