PMAXUD instruction (SSE4.1)

PMAXUD keeps the larger of each pair of doublewords, compared as unsigned integers, 4 results in an XMM register. It came with SSE4.1, part of x86-64-v2, and has no MMX form. On Zen 5, the recorded pmaxud xmm4, [mem] chose 80000000h over 0, where the signed PMAXSD keeps 0 because 80000000h is negative, and left bits 255:128 of the register as they were (see mixing SSE and AVX); pmaxud xmm4, xmm4 left the register unchanged. VPMAXUD, the VEX and EVEX form, covers the subtraction that stops at zero built from it, clamps and reductions, and VPMINUD the unsigned compares.

Before SSE4.1

SSE2 compares doublewords only as signed numbers, with PCMPGTD. Adding 80000000h to both sides, or subtracting it, which is the same modulo 2^32, flips their sign bits and maps the unsigned order onto the signed one. In our builds at -O2 for the x86-64 baseline, b[i] > c[i] ? b[i] : c[i] over uint32_t is:

GCC 14: PSUBD of 80000000h from both inputs, PCMPGTD, and a select with PAND, PANDN and POR;
Clang 23: the same with PXOR instead of PSUBD for the flip.

That is six instructions, copies aside, where -march=x86-64-v2 needs one PMAXUD with the second operand from memory, in both compilers. At -v2, the largest element of a uint32_t array accumulates with PMAXUD from a zeroed register, zero being the smallest unsigned value, with the last vector folded by PSRLDQ in GCC and PSHUFD in Clang. For b[i] > c[i] ? b[i] - c[i] : 0 at -v2, Clang subtracts c[i] from the maximum, as on the VPMAXUD page.

The legacy form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives PMAXUD one cycle, four per cycle.

Forms

Every encoding of PMAXUD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMAXUD xmm, m128` PMAXUD_XMMdq_MEMdq	`66 0F 38 3F /r`	SSE4.1
`PMAXUD xmm, xmm` PMAXUD_XMMdq_XMMdq	`66 0F 38 3F /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = max(xmm1.d[i], src2.d[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMAXUD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMAXUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_max_epu32` `__m128i _mm_max_epu32(__m128i __V1, __m128i __V2)`	`PMAXUD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Before SSE4.1#