PMINSB instruction (SSE4.1)

PMINSB keeps the smaller of each pair of bytes, compared as signed integers: 16 results in an XMM register, with no MMX form. On Zen 5, the recorded pminsb xmm12, xmm6 kept FFh over 01h (-1 over 1), 80h over FFh and 80h over 00h, the most negative byte winning every time, where the unsigned PMINUB would have kept 01h, FFh and 00h, and left bits 255:128 of the register as they were (see mixing SSE and AVX). It came with SSE4.1, part of x86-64-v2, together with its partner PMAXSB, whose page covers what the two share: the compare and select that the baseline needs instead, ReLU and clamping.

In compiled code

In our builds at -O2 with -march=x86-64-v2, over int8_t arrays:

Minimum. b[i] < c[i] ? b[i] : c[i] is one PMINSB per 16 bytes in GCC 14 and Clang 23, with the second operand from memory.
Smallest element. GCC folds the blocks into one register with PMINSB, then halves it with PSRLDQ by 8, 4, 2 and 1 and a PMINSB after each. Clang keeps two running minima, flips the sign bit of every byte with PXOR against 80h, which turns the signed order into the unsigned one, folds byte pairs into words with PSRLW and PMINUB, and finishes with PHMINPOSUW, SSE4.1’s horizontal minimum of words; PMINSW shows the same trick on words.
Without SSE4.1. For the baseline, both compilers compare with PCMPGTB and select with PAND, PANDN and POR, and reduce the same way, a compare and a select per step.

A clamp to an upper bound is a minimum: limiting int8_t values to 100 is PMINSB against a vector of 64h, and PMAXSB adds the lower bound.

The legacy form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives it one cycle, four per cycle. VPMINSB is the VEX and EVEX form.

Forms

Every encoding of PMINSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMINSB xmm, m128` PMINSB_XMMdq_MEMdq	`66 0F 38 38 /r`	SSE4.1
`PMINSB xmm, xmm` PMINSB_XMMdq_XMMdq	`66 0F 38 38 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 16 bytes in the xmm form.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(16):
    xmm1.b[i] = min(xmm1.sb[i], src2.sb[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMINSB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMINSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_epi8` `__m128i _mm_min_epi8(__m128i __V1, __m128i __V2)`	`PMINSB xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

In compiled code#