PMINSD instruction (SSE4.1)

PMINSD keeps the smaller of each pair of doublewords, compared as signed integers: 4 results in an XMM register, with no MMX form. On Zen 5, the recorded pminsd xmm7, xmm11 kept 00000000h over 00000001h and FFFFFFFFh over 00000001h (-1 over 1), the more negative doubleword winning, where the unsigned PMINUD would have kept 00000001h the second time, and left bits 255:128 of the register as they were (see mixing SSE and AVX). It came with SSE4.1, part of x86-64-v2, together with its partner PMAXSD, whose page covers what the two share: the compare and select the baseline needs instead, the ReLU and clamping idioms, and the Zen 5 latency. PMINSB covers the same across element sizes.

In compiled code

In our builds at -O2 with -march=x86-64-v2, over int32_t arrays:

Minimum. b[i] < c[i] ? b[i] : c[i] is one PMINSD per 4 doublewords in GCC 14 and Clang 23, both operands loaded by MOVDQU.
Clamping to an upper bound. b[i] < 1000 ? b[i] : 1000 is a single PMINSD against a broadcast constant; combined with a lower bound it adds a PMAXSD, as PMAXSD’s page shows.

Without SSE4.1, both compilers fall back to PCMPGTD and a select with PAND/PANDN/POR, the same four-instruction pattern PMAXSD’s page describes for the baseline.

The legacy form needs a memory operand aligned to 16 bytes. AMD’s latency spreadsheet for Zen 5 gives it one cycle, four per cycle. VPMINSD is the VEX and EVEX form, the latter with masking and a broadcast doubleword.

Forms

Every encoding of PMINSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMINSD xmm, m128` PMINSD_XMMdq_MEMdq	`66 0F 38 39 /r`	SSE4.1
`PMINSD xmm, xmm` PMINSD_XMMdq_XMMdq	`66 0F 38 39 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = min(xmm1.sd[i], src2.sd[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMINSD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMINSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_epi32` `__m128i _mm_min_epi32(__m128i __V1, __m128i __V2)`	`PMINSD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

In compiled code#