PMINSW instruction (SSE, SSE2)

PMINSW keeps the smaller of each pair of words, compared as signed 16-bit integers: 8 results in an XMM register, 4 in an MMX register. On Zen 5, the recorded pminsw xmm8, xmm15 kept FFFFh (-1) rather than 7FFFh and 8000h rather than 0000h, and left bits 255:128 of the register unchanged, as legacy SSE instructions do (see mixing SSE and AVX). Words are the only signed elements with a minimum in SSE2: the byte and doubleword forms, PMINSB and PMINSD, came with SSE4.1, and PMINUB, whose page describes the four SSE2 forms together, covers unsigned bytes.

In compiled code

GCC 14 and Clang 23 at -O2, for the SSE2 baseline:

Minimum and clamping. b[i] < c[i] ? b[i] : c[i] over int16_t is one PMINSW per 8 words, and clamping to -100..100 is a PMINSW and a PMAXSW against constant vectors, the order differing between the compilers. Intel’s optimization manual gives the same pair for clipping signed words (Section 6.6.6.1).
Reductions. For the smallest element of an int16_t array, GCC folds the blocks into one register, then halves it with PSRLDQ by 8, 4 and 2 and a PMINSW after each. With -march=x86-64-v2, Clang instead flips the sign bit of each word and lets PHMINPOSUW, which finds an unsigned minimum, finish in one step.
Unsigned words. PMINUW came with SSE4.1, so uint16_t needs a detour: Clang computes b - sat(b - c), a PSUBUSW and a PSUBW, which is c when b is the greater and b otherwise; GCC compares the saturated difference with zero and selects.
Absolute values. Before SSSE3’s PABSW, the absolute value of int16_t elements is the maximum of x and 0 - x, a PSUBW and a PMAXSW in both compilers.

Intel’s manual also notes that Skylake runs the MMX forms of PMINSW and PMAXSW at half the throughput of Broadwell, and shows the AVX2 form of a minimum and maximum search running several times faster (Section 15.16.5). AMD’s latency spreadsheet for Zen 5 gives the XMM form one cycle, four per cycle. The MMX form came with SSE, the XMM form with SSE2, and the legacy XMM form needs a memory operand aligned to 16 bytes. VPMINSW is the VEX and EVEX form.

In the optimization guide

What the optimization guide says about PMINSW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Skylake to Cooper Lake

Vectors on all parts: Many MMX instructions, among them the saturating additions and subtractions, comparisons, pmaxsw, pminsw, pavgb and pabsb, run on one port at half Broadwell’s rate.

Forms

Every encoding of PMINSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMINSW mm, m64` PMINSW_MMXq_MEMq	`NP 0F EA /r`	SSE
`PMINSW mm, mm` PMINSW_MMXq_MMXq	`NP 0F EA /r`	SSE
`PMINSW xmm, m128` PMINSW_XMMdq_MEMdq	`66 0F EA /r`	SSE2
`PMINSW xmm, xmm` PMINSW_XMMdq_XMMdq	`66 0F EA /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMINSW mm, mm/m64

for i in range(4):
    mm1.w[i] = min(mm1.sw[i], src2.sw[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMINSW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = min(xmm1.sw[i], src2.sw[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMINSW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMINSW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMINSW mm, mm/m64: mmx-mem
PMINSW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMINSW mm, mm/m64: may abort a TSX transaction
PMINSW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMINSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_epi16` `__m128i _mm_min_epi16(__m128i __a, __m128i __b)`	`PMINSW xmm, xmm` Legacy -msse2
`_mm_min_pi16` `__m64 _mm_min_pi16(__m64 __a, __m64 __b)`	`PMINSW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#