PMINUB instruction (SSE, SSE2)

PMINUB keeps the smaller of each pair of bytes, comparing them as unsigned numbers: 16 results in an XMM register, 8 in an MMX register. A minimum loop over uint8_t arrays compiles to it directly, at -O2 in both GCC 14 and Clang 23.

SSE2 offers only four of the twelve minimum and maximum instructions for bytes, words and doublewords: unsigned bytes (PMINUB and PMAXUB) and signed words (PMINSW and PMAXSW). The others, PMINSB, PMINUW, PMINUD and their kin, came with SSE4.1.

Unsigned comparisons

SSE2 has no unsigned byte comparison, but PMINUB supplies one: a <= b exactly where min(a, b) == a. For a loop setting r[i] to all ones where p[i] <= q[i], both compilers emit PMINUB and PCMPEQB, two instructions per 16 bytes. For a strict < they differ: Clang 23 takes PMAXUB, PCMPEQB and PANDN, while GCC 14 computes q[i] - p[i] with unsigned saturation (PSUBUSB), which is zero exactly where q[i] is not the greater, and compares that with zero. The method that works for any element size is to flip the top bit of both operands with PXOR, after which the signed PCMPGTB gives the unsigned answer. AVX-512BW finally has a direct unsigned comparison, VPCMPUB.

Other uses

Clamping. PMAXUB against the lower bound and PMINUB against the upper one clip bytes to any range; Intel’s optimization manual recommends the pair for unsigned bytes and PMINSW and PMAXSW for signed words (Section 6.6.6.1).
Finding a zero in several blocks. The minimum of several vectors has a zero byte exactly when one of them does, so a scan for a terminating zero can combine 32 or 64 bytes with PMINUB and test them with a single PCMPEQB against zero, then look at the blocks one by one only after a hit.

The MMX form came with SSE, the XMM form with SSE2, and the legacy XMM form needs a memory operand aligned to 16 bytes. VPMINUB is the VEX and EVEX form.

Forms

Every encoding of PMINUB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMINUB mm, m64` PMINUB_MMXq_MEMq	`NP 0F DA /r`	SSE
`PMINUB mm, mm` PMINUB_MMXq_MMXq	`NP 0F DA /r`	SSE
`PMINUB xmm, m128` PMINUB_XMMdq_MEMdq	`66 0F DA /r`	SSE2
`PMINUB xmm, xmm` PMINUB_XMMdq_XMMdq	`66 0F DA /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Result byte i comes from byte i of xmm1 and xmm2. Result bytes 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMINUB mm, mm/m64

for i in range(8):
    mm1.b[i] = min(mm1.b[i], src2.b[i])
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMINUB xmm, xmm/m128

for i in range(16):
    xmm1.b[i] = min(xmm1.b[i], src2.b[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMINUB mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMINUB xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMINUB mm, m64: mmx-mem
PMINUB mm, mm: none in XED
PMINUB xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMINUB mm, mm/m64: may abort a TSX transaction
PMINUB xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMINUB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_epu8` `__m128i _mm_min_epu8(__m128i __a, __m128i __b)`	`PMINUB xmm, xmm` Legacy -msse2
`_mm_min_pu8` `__m64 _mm_min_pu8(__m64 __a, __m64 __b)`	`PMINUB xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

Unsigned comparisons#

Other uses#