PMINUD instruction (SSE4.1)

PMINUD keeps the smaller of each pair of doublewords, compared as unsigned integers: 4 results in an XMM register. It is the SSE4.1 form of VPMINUD, whose page covers the unsigned compare built from AVX2’s signed-only VPCMPGTD, the saturating-add trick, and narrowing with VPACKUSDW; it has no MMX form. On Zen 5, the recorded pminud xmm0, xmm13 kept 1h over 80000000h at one element, where the signed PMINSD would have kept 80000000h (-2147483648, the smaller signed value there), and 80000000h over FFFFFFFFh at another, where the two agree because 80000000h is also the smaller unsigned value; it left bits 255:128 of the register as they were, as legacy SSE instructions do (see mixing SSE and AVX).

What the legacy form adds

SSE4.1 is part of x86-64-v2. The destination doubles as the first source, and the second operand is an XMM register or a 128-bit memory location that must be aligned to 16 bytes. Without SSE4.1, in our builds at -O2 over fixed-size uint32_t arrays, GCC 14 and Clang 23 flip the sign bit of both operands and compare with PCMPGTD, exactly as PMAXUD’s page shows for its mirror-image comparison, then select the smaller value with PAND, PANDN and POR.

AMD’s latency spreadsheet for Zen 5 gives PMINUD, like VPMINUD, one cycle and four per cycle.

Forms

Every encoding of PMINUD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMINUD xmm, m128` PMINUD_XMMdq_MEMdq	`66 0F 38 3B /r`	SSE4.1
`PMINUD xmm, xmm` PMINUD_XMMdq_XMMdq	`66 0F 38 3B /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm1 and xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = min(xmm1.d[i], src2.d[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMINUD xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMINUD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_epu32` `__m128i _mm_min_epu32(__m128i __V1, __m128i __V2)`	`PMINUD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

What the legacy form adds#