PMOVMSKB instruction (SSE, SSE2)

PMOVMSKB gathers the top bit of every byte into a general-purpose register: bit i of the result is bit 7 of byte i, which gives 16 bits from an XMM register and 8 from an MMX register, and every other bit of the destination is cleared. It is the bridge from vector comparisons to ordinary code. After PCMPEQB or PCMPGTB, whose results are FFh or 00h per byte, the mask says which bytes matched, and integer instructions take it from there:

Any, all, first, last. A test against zero tells whether any byte matched, a compare with FFFFh whether all did, TZCNT or BSF where the first match is and LZCNT or BSR the last. On a zero mask, TZCNT and LZCNT return the operand size, and BSF and BSR leave the destination unchanged (Intel’s manual adds that some older processors clear its upper half at a 32-bit size), so code tests for zero first.
Sign bits of raw data. Applied directly to data, it collects the bytes’ top bits: a zero result means that all 16 bytes are below 80h, which is a quick test for pure ASCII text.
Other element sizes. There is no word form. MOVMSKPS and MOVMSKPD take the top bit of each doubleword or quadword, of integer data as well, and words are first packed to bytes with saturation by PACKSSWB, which keeps each word’s sign.

VPMOVMSKB, the VEX form, gives 32 bits from a YMM register. AVX-512 has no EVEX form: its comparisons write mask registers directly, VPMOVB2M collects the top bits of bytes into one, and KMOVQ copies a mask to a general-purpose register.

Forms

Every encoding of PMOVMSKB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVMSKB r32, mm` PMOVMSKB_GPR32_MMXq	`NP 0F D7 /r`	SSE
`PMOVMSKB r32, xmm` PMOVMSKB_GPR32_XMMdq	`66 0F D7 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each byte of the source sets one bit of r32, bit i for byte i; the bits above them are cleared.

Shown: bytes 7 to 0. Every byte works alike: 8 and 16 bytes in the mm and xmm forms.

Bit i of r32 comes from byte i of xmm2. Result bits 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMOVMSKB r32, mm

r = 0
for i in range(8):
    r |= (mm2.sb[i] < 0) << i
dest.write(r)  # the other bits are cleared
# x87: TOP = 0, all tags valid

Run on AMD Zen 5 (EPYC 9645): 1 case.

PMOVMSKB r32, xmm

r = 0
for i in range(16):
    r |= (xmm2.sb[i] < 0) << i
dest.write(r)  # the other bits are cleared

Run on AMD Zen 5 (EPYC 9645): 1 case.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVMSKB r32, mm`
`r32`	explicit	write
`mm`	explicit	read
`PMOVMSKB r32, xmm`
`r32`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMOVMSKB r32, mm: mmx-nomem
PMOVMSKB r32, xmm: SSE_TYPE_7

Attributes

What else XED records about the forms. How to read.

PMOVMSKB r32, mm: may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVMSKB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movemask_epi8` `int _mm_movemask_epi8(__m128i __a)`	`PMOVMSKB r32, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions