PMOVSXBD instruction (SSE4.1)

PMOVSXBD is the SSE4.1 form of VPMOVSXBD, whose page covers the widening of signed bytes to doublewords and the two paths GCC and Clang take in loops, with and without SSE4.1. It widens the low four bytes of its source, copying each sign bit into the 24 bits above it. On Zen 5, pmovsxbd xmm1, xmm2 turned the bytes 01h, FFh, 7Fh and 80h into 00000001h, FFFFFFFFh, 0000007Fh and FFFFFF80h, and ignored the other twelve bytes of XMM2; pmovsxbd xmm4, dword ptr [mem] read four bytes, 00h, 00h, 01h and 01h.

What the legacy form adds

The memory operand is four bytes, not sixteen, with no alignment rule, so a loop can widen from any offset. For a loop copying int8_t values into int32_t ones, Clang 23 at -O2 with -march=x86-64-v2 does just that, pmovsxbd xmm0, dword ptr [rsi + rax], while GCC 14 widens in two steps through words with PMOVSXBW and PMOVSXWD.
The destination’s bits 128 and up keep their values, as the recorded cases show, where the VEX form clears them (see mixing SSE and AVX).
Before SSE4.1 there is no sign-extending move: the baseline code interleaves each byte with itself twice and shifts right arithmetically by 24 (PSRAD) in Clang, or builds sign bytes with PCMPGTB and unpacks with them in GCC.

AMD’s latency spreadsheet for Zen 5 lists PMOVSXBD as one macro-op with a latency of two cycles, on pipes FP1 and FP2, as for PMOVZXBD, which fills with zeros instead. PMOVSXBQ widens bytes to quadwords.

Forms

Every encoding of PMOVSXBD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVSXBD xmm, m32` PMOVSXBD_XMMdq_MEMd	`66 0F 38 21 /r`	SSE4.1
`PMOVSXBD xmm, xmm` PMOVSXBD_XMMdq_XMMd	`66 0F 38 21 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a doubleword, sign-extended, in the same order.

The grey upper part of each doubleword is the extension: copies of the sign bit.

Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = src2.sb[i]  # sign-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVSXBD xmm, xmm/m32`
`xmm`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVSXBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi8_epi32` `__m128i _mm_cvtepi8_epi32(__m128i __V)`	`PMOVSXBD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

What the legacy form adds#