PMOVSXBQ instruction (SSE4.1)

PMOVSXBQ widens the low two bytes of its source to quadwords, copying each byte’s sign bit into the 56 bits above it. It came with SSE4.1, together with PMOVZXBQ, which fills with zeros, and PMOVSXBW describes the signed family and its memory form, which reads two bytes at any alignment. On Zen 5, the recorded pmovsxbq xmm8, word ptr [mem] turned the bytes FFh and 01h into FFFFFFFFFFFFFFFFh and 0000000000000001h; it left bits 511:128 of ZMM8 alone, as legacy SSE instructions do.

Signed bytes to 64 bits

Signed 8-bit data, such as a small counter or a delta, reaches 64-bit arithmetic through this widening. In our builds at -O2 over fixed-size int8_t arrays widened into int64_t, with -march=x86-64-v2: Clang 23 widens two bytes at a time straight from memory. GCC 14 never emits PMOVSXBQ for this loop: it chains PMOVSXBW, PMOVSXWD and PMOVSXDQ instead, one step per doubling of width. At the SSE2 baseline GCC still vectorizes, building the sign bytes with PCMPGTB and interleaving data and signs with PUNPCKLBW and PUNPCKHBW, then repeating the same trick with PCMPGTW and PCMPGTD one step at a time, as PMOVSXBW’s page shows GCC doing for the first step alone; Clang 23 leaves this particular loop scalar, a MOVSBQ per byte.

AMD’s latency spreadsheet for Zen 5 lists PMOVSXBQ as one macro-op with a latency of two cycles, on pipes FP1 and FP2, as for PMOVZXBQ, which fills with zeros instead. VPMOVSXBQ is the VEX and EVEX form, which widens 4 or 8 bytes into a YMM or ZMM register.

Forms

Every encoding of PMOVSXBQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVSXBQ xmm, m16` PMOVSXBQ_XMMdq_MEMw	`66 0F 38 22 /r`	SSE4.1
`PMOVSXBQ xmm, xmm` PMOVSXBQ_XMMdq_XMMw	`66 0F 38 22 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a quadword, sign-extended, in the same order.

The grey upper part of each quadword is the extension: copies of the sign bit.

Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = src2.sb[i]  # sign-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVSXBQ xmm, xmm/m16`
`xmm`	explicit	write
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVSXBQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi8_epi64` `__m128i _mm_cvtepi8_epi64(__m128i __V)`	`PMOVSXBQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Signed bytes to 64 bits#