PMOVSXBW instruction (SSE4.1)

PMOVSXBW widens the low eight bytes of its source to words, copying each byte’s sign bit into the high byte: in the cases recorded on Zen 5, 80h became FF80h, FFh FFFFh and 7Fh 007Fh. It came with SSE4.1, together with PMOVZXBW, which fills with zeros; that page explains the memory form, which reads eight bytes at any alignment, and VPMOVSXBW is the VEX and EVEX form.

Before SSE4.1

SSE2 has no sign-extending move, and the compilers build one in two ways. For int8_t values copied into int16_t ones, at -O2 for the x86-64 baseline:

Clang 23 interleaves the bytes with themselves, punpcklbw xmm0, xmm0, so that each word holds the byte twice, and shifts the words right arithmetically by 8 with PSRAW, which leaves the byte in the low half and its sign in the high half. Both compilers keep this pair when it is written with intrinsics, even with SSE4.1 enabled.
GCC 14 computes the sign bytes with PCMPGTB, zero greater than each byte giving FFh for the negative ones, and interleaves data and signs with PUNPCKLBW and PUNPCKHBW, sixteen bytes into two registers of words.

With -msse4.1 both use PMOVSXBW: Clang straight from memory, eight bytes at a time, GCC from a sixteen-byte load, widening the upper half after moving it down with PSRLDQ. For that move in _mm_cvtepi8_epi16(_mm_srli_si128(x, 8)), Clang picks PSHUFD instead.

The way back

Narrowing words to bytes in SSE takes PACKSSWB, which saturates to -128 and 127 and packs two registers at a time, or, with SSSE3, a PSHUFB that keeps the low bytes; only AVX-512 has a truncating move in order, VPMOVWB. AMD’s Zen 5 guide lists PMOVSXBW as one macro-op with a latency of two cycles.

Forms

Every encoding of PMOVSXBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVSXBW xmm, m64` PMOVSXBW_XMMdq_MEMq	`66 0F 38 20 /r`	SSE4.1
`PMOVSXBW xmm, xmm` PMOVSXBW_XMMdq_XMMq	`66 0F 38 20 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a word, sign-extended, in the same order.

The grey upper half of each word is the extension: copies of the sign bit.

Result words 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    xmm1.w[i] = src2.sb[i]  # sign-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVSXBW xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVSXBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi8_epi16` `__m128i _mm_cvtepi8_epi16(__m128i __V)`	`PMOVSXBW xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Before SSE4.1#

The way back#