PMOVSXDQ instruction (SSE4.1)

PMOVSXDQ widens the low two doublewords of its source to quadwords, copying each sign bit into the 32 bits above it. On Zen 5, the recorded pmovsxdq xmm8, qword ptr [mem] turned 80000000h into FFFFFFFF80000000h and 7FFFFFFFh into 000000007FFFFFFFh, and pmovsxdq xmm4, xmm4 widened its own low half in place; both left bits 511:128 of their register alone. It came with SSE4.1, together with PMOVZXDQ, which fills with zeros, and PMOVSXBW describes the signed family and its memory form, which reads only the eight bytes it widens, at any alignment.

No shortcut in SSE2

Signed int values become int64_t ones in loops that copy them or sum them into a 64-bit total. The narrower sign extensions have an SSE2 shortcut: interleave the elements with themselves and shift right arithmetically, as PMOVSXWD’s page shows. For doublewords that would need an arithmetic shift of quadwords, which arrived only with AVX-512 (VPSRAQ). In our builds at -O2 for the baseline, GCC 14 and Clang 23 therefore build the sign halves with PCMPGTD, zero greater than each element giving FFFFFFFFh for the negative ones, and interleave data and signs with PUNPCKLDQ, GCC also with PUNPCKHDQ for the upper half of a 16-byte load.

With -march=x86-64-v2 the pair becomes one instruction: Clang widens two doublewords at a time straight from memory, and GCC widens both halves of a 16-byte load, the upper one after a shift by 8 bytes with PSRLDQ. In the sum, each widened pair goes to PADDQ. Both compilers fold _mm_cvtepi32_epi64(_mm_loadl_epi64(p)) into the memory form.

SSE has no instruction that packs quadwords back into doublewords; AVX-512 adds VPMOVQD, which truncates, and VPMOVSQD, which saturates. AMD’s latency spreadsheet for Zen 5 lists PMOVSXDQ as one macro-op with a latency of two cycles, on pipes FP1 and FP2. VPMOVSXDQ is the VEX and EVEX form, which widens 4 or 8 doublewords into a YMM or ZMM register.

Forms

Every encoding of PMOVSXDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVSXDQ xmm, m64` PMOVSXDQ_XMMdq_MEMq	`66 0F 38 25 /r`	SSE4.1
`PMOVSXDQ xmm, xmm` PMOVSXDQ_XMMdq_XMMq	`66 0F 38 25 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each doubleword becomes a quadword, sign-extended, in the same order.

The grey upper half of each quadword is the extension: copies of the sign bit.

Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = src2.sd[i]  # sign-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVSXDQ xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVSXDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi32_epi64` `__m128i _mm_cvtepi32_epi64(__m128i __V)`	`PMOVSXDQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

No shortcut in SSE2#