PMOVSXWD instruction (SSE4.1)

PMOVSXWD widens the low four words of its source to doublewords, copying each word’s sign bit into the 16 bits above it: on Zen 5, the recorded pmovsxwd xmm7, qword ptr [mem] turned 8000h into FFFF8000h and 000Fh into 0000000Fh, and pmovsxwd xmm0, xmm13 turned FFFFh into FFFFFFFFh; both left bits 511:128 of their register alone. It came with SSE4.1, together with PMOVZXWD, which fills with zeros, and PMOVSXBW describes the signed family and its memory form, which reads eight bytes at any alignment.

Words to int

Signed 16-bit data, such as audio samples, reaches 32-bit arithmetic through this widening. For a loop copying int16_t values into int32_t ones, in our builds at -O2:

With -march=x86-64-v2, Clang 23 widens four words at a time straight from memory, while GCC 14 widens both halves of a 16-byte load, the upper one after PSRLDQ by 8. For _mm_cvtepi16_epi32(_mm_srli_si128(x, 8)), Clang moves the upper half down with PSHUFD instead.
For the SSE2 baseline, Clang interleaves each word with itself, punpcklwd xmm0, xmm0, and shifts the doublewords right arithmetically by 16 with PSRAD, leaving the word in the low half and its sign in the high half. GCC computes the sign words with PCMPGTW, zero greater than each word, and interleaves data and signs with PUNPCKLWD and PUNPCKHWD.

Narrowing back is PACKSSDW, which saturates to -32768 and 32767 and packs two registers at a time. AMD’s latency spreadsheet for Zen 5 lists PMOVSXWD as one macro-op with a latency of two cycles, on pipes FP1 and FP2. VPMOVSXWD is the VEX and EVEX form, which widens 8 or 16 words into a YMM or ZMM register.

Forms

Every encoding of PMOVSXWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVSXWD xmm, m64` PMOVSXWD_XMMdq_MEMq	`66 0F 38 23 /r`	SSE4.1
`PMOVSXWD xmm, xmm` PMOVSXWD_XMMdq_XMMq	`66 0F 38 23 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each word becomes a doubleword, sign-extended, in the same order.

The grey upper half of each doubleword is the extension: copies of the sign bit.

Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = src2.sw[i]  # sign-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVSXWD xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVSXWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi16_epi32` `__m128i _mm_cvtepi16_epi32(__m128i __V)`	`PMOVSXWD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Words to int#