PMOVZXBD instruction (SSE4.1)

PMOVZXBD widens the low four bytes of its source to doublewords, each with 24 zero bits above it. It came with SSE4.1, and PMOVZXBW describes the family: a register form that reads only the low end of its source, and a memory form that reads only the bytes it widens, here four, at any alignment. On Zen 5, the recorded pmovzxbd xmm7, dword ptr [mem] turned the bytes 10h, 08h, 80h and 00h into 00000010h, 00000008h, 00000080h and 0, and pmovzxbd xmm1, xmm2 widened bytes 0 to 3 of XMM2 and ignored the other twelve; both left bits 511:128 of their register alone, as legacy SSE instructions do.

From bytes to int and float

Pixels and other byte data reach 32-bit arithmetic, or a conversion to float with CVTDQ2PS, through this widening. For loops copying uint8_t values into uint32_t or float ones, in our builds at -O2:

With -march=x86-64-v2, Clang 23 widens straight from memory, four bytes per PMOVZXBD. GCC 14 never uses it in these loops: it loads 16 bytes and widens in two steps, PMOVZXBW to words and PMOVZXWD to doublewords, moving upper halves down with PSRLDQ by 8, as it does for the signed VPMOVSXBD. Both fold _mm_cvtepu8_epi32(_mm_cvtsi32_si128(*(const int *)p)) into the memory form.
For the SSE2 baseline, the widening takes two interleaves with a zeroed register, PUNPCKLBW and then PUNPCKLWD. Clang loads four bytes at a time with MOVD and unpacks only low halves; GCC widens a 16-byte load into four registers with six unpacks, low and high.

AMD’s latency spreadsheet for Zen 5 lists PMOVZXBD as one macro-op with a latency of two cycles, on pipes FP1 and FP2. PMOVSXBD sign-extends instead, PMOVZXBQ widens bytes to quadwords, and VPMOVZXBD is the VEX and EVEX form, which widens 8 or 16 bytes into a YMM or ZMM register.

Forms

Every encoding of PMOVZXBD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXBD xmm, m32` PMOVZXBD_XMMdq_MEMd	`66 0F 38 31 /r`	SSE4.1
`PMOVZXBD xmm, xmm` PMOVZXBD_XMMdq_XMMd	`66 0F 38 31 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a doubleword, zero-extended, in the same order.

The grey upper part of each doubleword is the extension: zeros.

Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = src2.b[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXBD xmm, xmm/m32`
`xmm`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu8_epi32` `__m128i _mm_cvtepu8_epi32(__m128i __V)`	`PMOVZXBD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

From bytes to int and float#