PMOVZXBQ instruction (SSE4.1)

PMOVZXBQ widens the low two bytes of its source to quadwords, each with 56 zero bits above it. It came with SSE4.1, and PMOVZXBW describes the family: a register form that reads only the low end of its source, and a memory form that reads only the two bytes it widens, at any alignment. On Zen 5, the recorded pmovzxbq xmm7, word ptr [mem] turned the bytes FFh and 7Fh into 00000000000000FFh and 000000000000007Fh, and pmovzxbq xmm4, xmm4 widened its own bytes 0 and 1, 7Fh and 80h, into 000000000000007Fh and 0000000000000080h, not the all-ones quadword a sign extension would give for 80h; both left bits 511:128 of their register alone, as legacy SSE instructions do.

Two bytes to two quadwords

Narrow unsigned data widens to 64 bits where it feeds pointer arithmetic or a 64-bit sum that cannot overflow. In our builds at -O2 with -march=x86-64-v2, over fixed-size uint8_t arrays widened into uint64_t: Clang 23 widens two bytes at a time straight from memory, folding _mm_cvtepu8_epi64(_mm_loadl_epi64(p)) into the single memory form. GCC 14 never emits PMOVZXBQ for this loop at all: it widens bytes to words with PMOVZXBW, those words to doublewords with PMOVZXWD, and finally to quadwords with PMOVZXDQ, one chain of narrower moves instead of the direct one. For the SSE2 baseline, GCC 14 still vectorizes, with three interleaves against a zeroed register, PUNPCKLBW, PUNPCKLWD and PUNPCKLDQ; Clang 23 instead leaves the loop scalar, a MOVZBL and a MOVQ per byte.

AMD’s latency spreadsheet for Zen 5 lists PMOVZXBQ as one macro-op with a latency of two cycles, on pipes FP1 and FP2. PMOVSXBQ sign-extends instead, and VPMOVZXBQ is the VEX and EVEX form, which widens 4 or 8 bytes into a YMM or ZMM register.

Forms

Every encoding of PMOVZXBQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXBQ xmm, m16` PMOVZXBQ_XMMdq_MEMw	`66 0F 38 32 /r`	SSE4.1
`PMOVZXBQ xmm, xmm` PMOVZXBQ_XMMdq_XMMw	`66 0F 38 32 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a quadword, zero-extended, in the same order.

The grey upper part of each quadword is the extension: zeros.

Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = src2.b[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXBQ xmm, xmm/m16`
`xmm`	explicit	write
`xmm/m16`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXBQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu8_epi64` `__m128i _mm_cvtepu8_epi64(__m128i __V)`	`PMOVZXBQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Two bytes to two quadwords#