PMOVZXBW instruction (SSE4.1)

PMOVZXBW is SSE4.1’s widening of unsigned bytes: the low eight bytes of the source become eight words, each with a zero high byte, so 80h becomes 0080h and FFh 00FFh, as the cases recorded on Zen 5 show. VPMOVZXBW, the VEX and EVEX form, covers its use in widening loops and how it differs from the unpack instructions in 256-bit registers; this page adds what is particular to the legacy encoding.

Eight bytes, at any address

The memory form reads exactly eight bytes, not sixteen, and like other legacy SSE operands smaller than sixteen bytes it has no alignment rule (its exceptions are of type 5). A widening loop can therefore take its input straight from memory at any offset. For a loop that copies uint8_t values into uint16_t ones, Clang 23 at -O2 with -msse4.1 does just that, pmovzxbw xmm0, qword ptr [rsi + rax], eight bytes per instruction. GCC 14 loads sixteen bytes and widens each half from a register. Both compilers fold _mm_cvtepu8_epi16(_mm_loadl_epi64(p)) into the single memory form.

The register form reads only bits 63:0 of its source. To widen the upper eight bytes, the code first moves them down, with PSRLDQ by 8 or PSHUFD, or uses PUNPCKHBW against a zeroed register, the SSE2 way.

Like other legacy SSE instructions, it leaves bits 128 and up of the destination unchanged, as the recorded cases show; the VEX form clears them. PMOVSXBW sign-extends instead, and PMOVZXBD and PMOVZXBQ widen bytes further. AMD’s Zen 5 guide lists PMOVZXBW as one macro-op with a latency of two cycles.

Forms

Every encoding of PMOVZXBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXBW xmm, m64` PMOVZXBW_XMMdq_MEMq	`66 0F 38 30 /r`	SSE4.1
`PMOVZXBW xmm, xmm` PMOVZXBW_XMMdq_XMMq	`66 0F 38 30 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a word, zero-extended, in the same order.

The grey upper half of each word is the extension: zeros.

Result words 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(8):
    xmm1.w[i] = src2.b[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXBW xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu8_epi16` `__m128i _mm_cvtepu8_epi16(__m128i __V)`	`PMOVZXBW xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Eight bytes, at any address#