PMOVZXDQ instruction (SSE4.1)

PMOVZXDQ widens the low two doublewords of its source to quadwords, each with a zero high half. On Zen 5, the recorded pmovzxdq xmm4, qword ptr [mem] turned FFFFFFFFh into 00000000FFFFFFFFh and 1 into 1, and pmovzxdq xmm1, xmm2 widened doublewords 0 and 1 of XMM2 and ignored the other two; both left bits 511:128 of their register alone, as legacy SSE instructions do. It came with SSE4.1, and PMOVZXBW describes the family: the memory form reads only the eight bytes it widens, at any alignment.

Unsigned 32-bit values in 64 bits

The result is what PUNPCKLDQ gives with a zeroed second operand, which is how code without SSE4.1 does it. Widening uint32_t values to uint64_t happens in loops that copy them or sum them into a 64-bit total, which cannot overflow. In our builds at -O2:

With -march=x86-64-v2, Clang 23 widens straight from memory, two doublewords per PMOVZXDQ, and adds with PADDQ. GCC 14 loads 16 bytes, widens the low half, and moves the high half down with PSRLDQ by 8 for a second PMOVZXDQ.
For the SSE2 baseline, GCC interleaves a 16-byte load with a zeroed register, PUNPCKLDQ for the low half and PUNPCKHDQ for the high one. Clang does the same with eight-byte loads and PUNPCKLDQ in the sum, but in the copy loop it loads with MOVSD and interleaves with UNPCKLPS, the floating-point twin, which moves the same bits.

Both compilers fold _mm_cvtepu32_epi64(_mm_loadl_epi64(p)) into the memory form. AMD’s latency spreadsheet for Zen 5 lists PMOVZXDQ as one macro-op with a latency of two cycles, on pipes FP1 and FP2. PMOVSXDQ sign-extends instead, and VPMOVZXDQ is the VEX and EVEX form, which widens 4 or 8 doublewords into a YMM or ZMM register.

Forms

Every encoding of PMOVZXDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXDQ xmm, m64` PMOVZXDQ_XMMdq_MEMq	`66 0F 38 35 /r`	SSE4.1
`PMOVZXDQ xmm, xmm` PMOVZXDQ_XMMdq_XMMq	`66 0F 38 35 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each doubleword becomes a quadword, zero-extended, in the same order.

The grey upper half of each quadword is the extension: zeros.

Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = src2.d[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXDQ xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu32_epi64` `__m128i _mm_cvtepu32_epi64(__m128i __V)`	`PMOVZXDQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Unsigned 32-bit values in 64 bits#