PMOVZXWD instruction (SSE4.1)

PMOVZXWD widens the low four words of its source to doublewords, each with a zero high half: on Zen 5, the recorded pmovzxwd xmm0, qword ptr [mem] turned FFFFh into 0000FFFFh and 7FFFh into 00007FFFh, and left bits 511:128 of ZMM0 alone, as legacy SSE instructions do. It came with SSE4.1. PMOVZXBW describes the family: a memory form that reads only the eight bytes it widens, at any alignment, and a register form that reads only bits 63:0, so the upper half of a vector has to be moved down first.

From uint16_t to uint32_t

For a loop copying uint16_t values into uint32_t ones, in our builds at -O2:

With -march=x86-64-v2, Clang 23 widens straight from memory, four words per PMOVZXWD. GCC 14 loads 16 bytes, widens the low half from the register, and moves the high half down with PSRLDQ by 8 for a second PMOVZXWD. Both fold _mm_cvtepu16_epi32(_mm_loadl_epi64(p)) into the memory form.
For the SSE2 baseline, the zero extension is an interleave with a zeroed register: GCC widens both halves of a 16-byte load with PUNPCKLWD and PUNPCKHWD, Clang loads eight bytes at a time with MOVQ and uses PUNPCKLWD alone.

The same widening appears where a C expression on uint16_t needs 32-bit arithmetic, such as a shift by a count held in a variable, which C performs on int: with x86-64-v2 both compilers widen with PMOVZXWD, shift doublewords and narrow the result again with PACKUSDW.

AMD’s latency spreadsheet for Zen 5 lists PMOVZXWD as one macro-op with a latency of two cycles, on pipes FP1 and FP2. PMOVSXWD sign-extends instead, PMOVZXWQ widens words to quadwords, and VPMOVZXWD is the VEX and EVEX form, which widens 8 or 16 words into a YMM or ZMM register.

Forms

Every encoding of PMOVZXWD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXWD xmm, m64` PMOVZXWD_XMMdq_MEMq	`66 0F 38 33 /r`	SSE4.1
`PMOVZXWD xmm, xmm` PMOVZXWD_XMMdq_XMMq	`66 0F 38 33 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each word becomes a doubleword, zero-extended, in the same order.

The grey upper half of each doubleword is the extension: zeros.

Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = src2.w[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXWD xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu16_epi32` `__m128i _mm_cvtepu16_epi32(__m128i __V)`	`PMOVZXWD xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

From uint16_t to uint32_t#