PMOVZXWQ instruction (SSE4.1)

PMOVZXWQ widens the low two words of its source to quadwords, each with a zero high 48 bits. It came with SSE4.1, and PMOVZXBW describes the family: a register form that reads only the low four bytes of its source, and a memory form that reads only the four bytes it widens, at any alignment. On Zen 5, the recorded pmovzxwq xmm1, dword ptr [mem] turned the words 0000h and 0001h into 0000000000000000h and 0000000000000001h, and pmovzxwq xmm4, xmm4 widened its own words 0 and 1, 0000h and 000Fh, the same way; both left bits 511:128 of their register alone, as legacy SSE instructions do. PMOVSXWQ’s page shows the same width sign-extended instead, where a word with its top bit set would turn into a quadword of mostly ones rather than staying small.

Two words to two quadwords

Narrow unsigned data, such as a count or an index read from a compact format, widens to 64 bits where pointer arithmetic or a 64-bit sum needs it. In our builds at -O2 over fixed-size uint16_t arrays widened into uint64_t, with -march=x86-64-v2: Clang 23 widens two words at a time straight from memory, folding _mm_cvtepu16_epi64(_mm_loadl_epi64(p)) into the single memory form. GCC 14 never emits PMOVZXWQ for this loop: it widens to doublewords with PMOVZXWD first and reaches quadwords with PMOVZXDQ, one chain of narrower moves instead of the direct one. At the SSE2 baseline both compilers vectorize the same way, with two interleaves against a zeroed register, PUNPCKLWD and then PUNPCKLDQ.

AMD’s latency spreadsheet for Zen 5 lists PMOVZXWQ as one macro-op with a latency of two cycles, on pipes FP1 and FP2. VPMOVZXWQ is the VEX and EVEX form, which widens 4 or 8 words into a YMM or ZMM register.

Forms

Every encoding of PMOVZXWQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMOVZXWQ xmm, m32` PMOVZXWQ_XMMdq_MEMd	`66 0F 38 34 /r`	SSE4.1
`PMOVZXWQ xmm, xmm` PMOVZXWQ_XMMdq_XMMd	`66 0F 38 34 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each word becomes a quadword, zero-extended, in the same order.

The grey upper part of each quadword is the extension: zeros.

Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.q[i] = src2.w[i]  # zero-extended
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMOVZXWQ xmm, xmm/m32`
`xmm`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMOVZXWQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepu16_epi64` `__m128i _mm_cvtepu16_epi64(__m128i __V)`	`PMOVZXWQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Two words to two quadwords#