PMULDQ instruction (SSE4.1)

PMULDQ multiplies signed doublewords into full 64-bit products, but only the even-numbered ones: the low doubleword of each quadword of the destination times the low doubleword of the matching quadword of the source, two products in an XMM register. It is the signed partner of SSE2’s PMULUDQ, whose page covers the uses the two share, and came with SSE4.1, part of x86-64-v2, without an MMX form. On Zen 5, the recorded pmuldq xmm8, xmm15 multiplied 1 by 1 and 0 by 7FFFFFFFh into the quadwords 1 and 0, although the upper doublewords held 80000000h and FFFFFFFFh: they play no part. Its VEX form, VPMULDQ, has the recorded cases with negative numbers, and the legacy form keeps bits 255:128 of its register (see mixing SSE and AVX).

Without and with SSE4.1

In our builds at -O2 over int32_t arrays:

Widening products. a[i] = (int64_t)b[i] * c[i] stays scalar for the baseline in GCC 14 and Clang 23, with MOVSXD and IMUL. With -march=x86-64-v2 both use PMULDQ: GCC spreads the inputs over the even positions with PUNPCKLDQ and PUNPCKHDQ of a register with itself, and Clang widens them with PMOVZXDQ, a zero extension, which is enough because PMULDQ reads only the low halves. A sum of the products adds them with PADDQ.
Division by a constant. a[i] = b[i] / 7 needs the high halves of signed products by 92492493h. For the baseline, Clang takes unsigned ones from PMULUDQ and corrects them for the negative elements, found with PCMPGTD against zero, by a PAND and a PSUBD; GCC builds full products of the sign-extended inputs, three PMULUDQs for every two of them. At -v2, both multiply twice per vector with PMULDQ, the even elements and the odd ones moved down, and join the high doublewords with PBLENDW.

AMD’s latency spreadsheet for Zen 5 gives PMULDQ what it gives PMULUDQ: 3 cycles, two per cycle, on pipes FP0 and FP1. A memory operand must be aligned to 16 bytes.

Forms

Every encoding of PMULDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULDQ xmm, m128` PMULDQ_XMMdq_MEMdq	`66 0F 38 28 /r`	SSE4.1
`PMULDQ xmm, xmm` PMULDQ_XMMdq_XMMdq	`66 0F 38 28 /r`	SSE4.1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The even doublewords only: doublewords 2 and 0 of the sources make quadwords 1 and 0 of the result, and so on.

Result quadword i comes from doubleword 2i of xmm1 and xmm2. Result quadwords 1 to 0: a2, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    sa = xmm1.sd[2 * i]
    sb = src2.sd[2 * i]
    xmm1.q[i] = sa * sb
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULDQ xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mul_epi32` `__m128i _mm_mul_epi32(__m128i __V1, __m128i __V2)`	`PMULDQ xmm, xmm` Legacy -msse4.1

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE4` SSE4.1	SSE4.1 `CPUID.01H:ECX[19]` SSE4.1	Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6 Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

More SSE4.1 instructions

All 49 SSE4.1 instructions

Without and with SSE4.1#