PMULHRSW

PMULHRSW multiplies signed words and keeps bits 30:15 of each 32-bit product after adding 4000h to it: the product of two Q15 fractions, rounded to the nearest Q15 value. VPMULHRSW, the VEX and EVEX form, explains the format, the one overflow (8000h times 8000h gives 8000h again) and the uses; this page adds what concerns the SSSE3 encodings.

Where it fits#

Unlike PMADDUBSW, the other SSSE3 multiply, it treats both operands alike, so swapping them changes nothing. The legacy form still overwrites its first operand, and a compiler copies a register when both inputs stay in use. PMULHW is the plain high half without the rounding.

A case recorded on Zen 5 with the MMX form shows the rounding on a negative product: 8000h times 7FFFh, -1 times 0.99997, gave 8001h, -0.99997, the exact product rounded to Q15. Products smaller than half a Q15 step, such as 1 times 1 or -1 times -1 in the recorded XMM case, round to zero.

Forms and compilers#

• The XMM form needs SSSE3, part of x86-64-v2, and a memory operand aligned to 16 bytes.
• The MMX form takes four words and changes the x87 state as every MMX instruction does (see MOVD). Its intrinsic, _mm_mulhrs_pi16, compiles to the XMM form in GCC 14 and Clang 23.

GCC 14 at -O2 vectorizes a loop of (int16_t)((((int32_t)a[i] * b[i] >> 14) + 1) >> 1) over int16_t arrays to PMULHRSW with -mssse3 or -march=x86-64-v2, as long as it knows that the output does not overlap the inputs (restrict); without that it stays scalar. Clang 23 does not recognize the loop and needs _mm_mulhrs_epi16.

AMD’s Zen 5 guide lists PMULHRSW with a latency of three cycles, as for the other word multiplies.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    sa = mm1.sw[i]
    sb = src2.sw[i]
    mm1.w[i] = (sa * sb >> 14) + 1 >> 1
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

for i in range(8):
    sa = xmm1.sw[i]
    sb = src2.sw[i]
    xmm1.w[i] = (sa * sb >> 14) + 1 >> 1
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMULHRSW mm, mm/m64

mmx-mem

PMULHRSW xmm, xmm/m128

SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMULHRSW mm, mm/m64

may abort a TSX transaction

PMULHRSW xmm, m128

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULHRSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSSE3 instructions

• PABSB
• PABSD
• PABSW
• PALIGNR
• PHADDD
• PHADDSW
• PHADDW
• PHSUBD
• PHSUBSW
• PHSUBW
• PMADDUBSW
• PSHUFB
• PSIGNB
• PSIGND
• PSIGNW