PMULHUW instruction (SSE, SSE2)

PMULHUW multiplies unsigned words and keeps the high 16 bits of each 32-bit product: 8 results in an XMM register, 4 in an MMX register. It is the unsigned twin of PMULHW, whose page shows how the high and low halves combine; PMULLW gives the low half, which is the same for signed and unsigned words. Only the high half tells the two apart. On Zen 5, the recorded pmulhuw mm3, mm3 turned FFFFh times FFFFh into FFFEh, the top of FFFE0001h, where PMULHW, reading -1 times -1, gives 0000h; and pmulhuw xmm12, xmmword ptr [mem] gave 3FFFh for 8000h times 7FFFh.

Multiplying by a fraction

The high half of x * c is x * c / 65536 rounded down, so one PMULHUW multiplies 16-bit values by any fraction c / 65536. In our builds at -O2 for the x86-64 baseline, over arrays of uint16_t:

(x * 49152u) >> 16, three quarters of x, is a single PMULHUW by C000h in GCC 14 and Clang 23.
x / 10 is PMULHUW by CCCDh followed by PSRLW by 3: CCCDh / 2^19 is just above one tenth, close enough to give the exact quotient for every 16-bit x.
x / 7 needs a 17-bit multiplier. Both compilers multiply by 2493h, then add back the part that does not fit: the high half h is subtracted from x, the difference halved with PSRLW, h added and the sum shifted right by 2.

Full products

For (uint32_t)a[i] * b[i], both compilers compute the low halves with PMULLW and the high halves with PMULHUW and interleave them into doublewords: GCC with PUNPCKLWD and PUNPCKHWD on full registers, Clang with PUNPCKLWD alone on four words loaded at a time. SSE2 has no unsigned word form of PMADDWD, the trick Clang uses for signed words, so the pair is the way here.

AMD’s latency spreadsheet for Zen 5 gives the XMM form three cycles, two per cycle on pipes FP0 and FP1. The MMX form came with SSE rather than MMX and the XMM form with SSE2; the legacy XMM form keeps bits 255:128 of its register (see mixing SSE and AVX) and needs a memory operand aligned to 16 bytes. VPMULHUW is the VEX and EVEX form.

Forms

Every encoding of PMULHUW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`PMULHUW mm, m64` PMULHUW_MMXq_MEMq	`NP 0F E4 /r`	SSE
`PMULHUW mm, mm` PMULHUW_MMXq_MMXq	`NP 0F E4 /r`	SSE
`PMULHUW xmm, m128` PMULHUW_XMMdq_MEMdq	`66 0F E4 /r`	SSE2
`PMULHUW xmm, xmm` PMULHUW_XMMdq_XMMdq	`66 0F E4 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each word of the result comes from the word in the same place in each source.

Every word works alike: 4 and 8 words in the mm and xmm forms.

Result word i comes from word i of xmm1 and xmm2. Result words 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

PMULHUW mm, mm/m64

for i in range(4):
    mm1.w[i] = mm1.w[i] * src2.w[i] >> 16
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

PMULHUW xmm, xmm/m128

for i in range(8):
    xmm1.w[i] = xmm1.w[i] * src2.w[i] >> 16
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`PMULHUW mm, mm/m64`
`mm`	explicit	read, write
`mm/m64`	explicit	read
`PMULHUW xmm, xmm/m128`
`xmm`	explicit	read, write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

PMULHUW mm, m64: mmx-mem
PMULHUW mm, mm: none in XED
PMULHUW xmm, xmm/m128: SSE_TYPE_4

Attributes

What else XED records about the forms. How to read.

PMULHUW mm, mm/m64: may abort a TSX transaction
PMULHUW xmm, m128: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to PMULHUW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_mulhi_epu16` `__m128i _mm_mulhi_epu16(__m128i __a, __m128i __b)`	`PMULHUW xmm, xmm` Legacy -msse2
`_mm_mulhi_pu16` `__m64 _mm_mulhi_pu16(__m64 __a, __m64 __b)`	`PMULHUW xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

More SSE2 instructions

All 124 SSE2 instructions

Multiplying by a fraction#

Full products#